22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB
edge and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
2. Port-B size is word or byte; tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively. (The word-size case is shown.)
Figure 14.
FFAFFA
FFAFFA
FFA
Flag Timing and First Available Write when FIFO1 is Full
EFB
RENB
B0 - B17
CLKB
FFA
CLKA
CSA
3520 drw14
WRA
12
A0 - A35
ENA
t
CLK
t
CLKH
t
CLKL
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS
t
DS
t
ENH
t
DH
To FIFO1
Read 2
HIGH
LOW
HIGH
(1)
FIFO1 Full
t
WFF
t
WFF
Read 1
t
A
t
EN
Previous Word in
FIFO1 Output Register
t
ENH
t
DIS
t
ENS
Figure 13.
EFAEFA
EFAEFA
EFA
Flag Timing and First Data Read when FIFO2 is Empty
FFC
C0 - C17
CLKA
EFA
CSA
W/RA
WENC
ENA
A0 -A35
CLKC
12
3520 drw13
t
CLKH
t
CLKL
t
CLK
t
ENS
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKL
t
ENS
t
ENH
t
A
W1
FIFO2 Empty
LOW
LOW
t
CLKH
HIGH
(1)
t
REF
t
REF
t
DS
t
DH
Write 1
Write 2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC
edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
2. Port-C size is word or byte; tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively. (The word-size case is shown.)
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
AEB
CLKA
RENB
3520 drw16
ENA
CLKB
2
1
tENS tENH
tSKEW2
tPAE
tPAE
tENS tENH
X Long Word in FIFO1
(X+1) Long Words in FIFO1
(1)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA
edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH).
3. Port-B size is word or byte; AEB is set LOW by the last word or byte read of the long word, respectively.
Figure 16. Timing for AEB when FIFO1 is Almost-Empty
Figure 17. Timing for
AEAAEA
AEAAEA
AEA
when FIFO2 is Almost-Empty
AEA
CLKC
ENA
3520 drw17
WENC
CLKA
2
1
t
ENS
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS
t
ENH
(X+1) Long Words in FIFO2
X Long Words in FIFO2
(1)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge
and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 read (CSA = LOW, W/RA = LOW).
3. Port-C size is word or byte; tSKEW2 is referenced from the rising CLKC edge that writes the last word or byte of the long word, respectively.
CSA
EFA
ENA
A0 - A35
CLKA
FFC
CLKC
3520 drw15
12
C0 - C17
WENC
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS
t
DS
t
ENH
t
DH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
LOW
W/RA
LOW
HIGH
(1)
FIFO2 Full
t
WFF
t
WFF
t
DH
t
DS
Figure 15.
FFCFFC
FFCFFC
FFC
Flag Timing and First Available Write when FIFO2 is Full
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
2. Port-C size is word or byte; FFC is set LOW by the last word or byte write of the long word, respectively. (The word-size case is shown.)
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
AFA
CLKA
RENB
3520 drw18
ENA
CLKB
1
2
tSKEW2
tENS
tENH
tPAF
tENS tENH
tPAF
[64-(X+1)] Long Words in FIFO1
(64-X) Long Words in FIFO1
(1)
NOTES:
1. t
SKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA
edge and rising CLKB edge is less than t
SKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH).
3. Port-B size is word or byte; t
SKEW2 is referenced from the last word or byte read of the long word, respectively.
Figure 18. Timing for
AFAAFA
AFAAFA
AFA
when FIFO1 is Almost-Full
Figure 20. ODD/EVEN, W/
RR
RR
R
A and PGA to
PEFAPEFA
PEFAPEFA
PEFA
Timing
AFC
CLKC
ENA
3520drw19
WENC
CLKA
12
tSKEW2
tENS
tENH
tPAF
tENS
tENH
tPAF
[64-(X+1)] Long Words in FIFO2
(64-X) Long Words in FIFO2
(1)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between the rising
CLKC edge and rising CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKA cycle later than shown.
2. Port-C size is word or byte; AFC is set LOW by the last word or byte read of the long word, respectively.
Figure 19. Timing for
AFCAFC
AFCAFC
AFC
when FIFO2 is Almost-Full
3520 drw20
ODD/
EVEN
PEFA
PGA
W/RA
Valid Valid
Valid Valid
t
POPE
t
PEPE
t
POPE
t
PEPE
3520 drw21
ODD/
EVEN
PEFC
Valid Valid
Valid
t
POPE
t
POPE
Figure 21. ODD/
EVENEVEN
EVENEVEN
EVEN
to
PEFCPEFC
PEFCPEFC
PEFC
Timing

723616L15PFG

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 64 X 36 X 2 FIFO
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet