723616L15PFG Datasheet 723616L15PFG, 723616L15PFG8 | P10-P12

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723616 CMOS TRIPLE BUS SyncFIFO

™™

™ WITH

BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

TABLE 4 — PORT-C ENABLE FUNCTION TABLE

NOTE:

1. At no time during the operation of the FIFO is it permissible to apply a LOW logic level simultaneously to both SIZ0 and SIZ1, nor is it permissible to apply a HIGH logic level

simultaneously to both these inputs. These state combinations are reserved.

WENC SIZ1, SIZ0 CLKC C0-C17 Inputs Port Functions

L X X In High-Impedance State None

H One or the other LOW

(1)

↑ In High-Impedance State FIFO2 write

SIGNAL DESCRIPTIONS

RESET

The IDT723616 is reset by taking the reset (RST) input LOW for at least

four Port A clock (CLKA), four Port B clock (CLKB) and four Port C clock

(CLKC) LOW-to-HIGH transitions. The reset input can switch asynchro-

nously to the clocks. A device reset initializes the internal read and write

pointers of each FIFO and forces the full flags (FFA, FFC) LOW, the empty

flags (EFA, EFB) LOW, the Almost-Empty flags (AEA, AEB) LOW and the

Almost-Full flags (AFA, AFC) HIGH. After a reset, FFA is set HIGH after

two LOW-to-HIGH transitions of CLKA and FFC is set HIGH after two

LOW-to-HIGH transitions of CLKC. The device must be reset after power

up before data is written to its memory.

A LOW-to-HIGH transition on the RST input loads the Almost-Full and

Almost-Empty Offset register (X) with the values selected by the flag-

select (FS0, FS1) inputs. The values that can be loaded into the registers

are shown in Table 1.

TABLE 2 — PORT-A ENABLE FUNCTION TABLE

FIFO WRITE/READ OPERATION

The state of Port A data A0-A35 outputs is controlled by the Port A chip

select (CSA) and the Port A write/read select (W/RA). The A0-A35 outputs are

in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35

outputs are active when both CSA and W/RA are LOW. Data is loaded into

FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when

CSA is LOW, W/RA is HIGH, ENA is HIGH, and FFA is HIGH. Data is read

from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when

CSA is LOW, W/RA is LOW, ENA is HIGH, and EFA is HIGH (see Table 2).

The state of the Port B data (B0-B17) outputs is controlled by Port B read

select (RENB). The B0-B17 outputs are in the high-impedance state when

REN is LOW. The B0-B17 outputs are active when REN IS HIGH. Data is

read from FIFO1 to the B0-B17 outputs by a LOW-to-HIGH transition of

CLKB when RENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW

(see Table 3).

Data is loaded into FIFO2 from the C0-C17 inputs on a LOW-to-HIGH

transition of CLKC when WENC is HIGH, FFC is HIGH, and either SIZ0 or

SIZ1 is LOW (see Table 4).

The setup and hold time constraints to the Port Clocks for the Port A chip select

(CSA) and write/read selects (W/RA, RENB, WENC) are only for enabling

write and read operations and are not related to high-impedance control of the

data outputs. If a port enable is LOW during a clock cycle, the Port Chip select

(for Port A) and write/read select (for all ports) can change states during the

setup and hold time window of the cycle.

TABLE 1 — FLAG PROGRAMMING

TABLE 3 — PORT-B ENABLE FUNCTION TABLE

NOTE:

1. At no time during the operation of the FIFO is it permissible to apply a LOW logic level simultaneously to both SIZ0 and SIZ1, nor is it permissible to apply a HIGH logic level

simultaneously to both these inputs. These state combinations are reserved.

ALMOST-FULL AND

FS1 FS0 RST ALMOST-EMPTY FLAG

OFFSET REGISTER (X)

HH↑ 16

HL↑ 12

LH↑ 8

LL↑ 4

CSA W/RA ENA CLKA A0-A35 Outputs Port Functions

H X X X In High-Impedance State None

L H L X In High-Impedance State None

LHH↑ In High-Impedance State FIFO1 Write

L L L X Active, FIFO2 Output Register None

LLH↑ Active, FIFO2 Output Register FIFO2 Read

RENB SIZ1, SIZ0 CLKB B0-B17 Outputs Port Functions

L X X In High-Impedance State None

H One or the other LOW

(1)

↑ Active, FIFO1 Output Register FIFO1 read

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723616 CMOS TRIPLE BUS SyncFIFO

™™

™ WITH

BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

SYNCHRONIZED FIFO FLAGS

Each FIFO is synchronized to its Port Clock through two flip-flop stages. This

is done to improve flag reliability by reducing the probability of metastable

events on the output when CLKA operates asynchronously relative to CLKB

or CLKC. EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB and AEB

are synchronized to CLKB. FFC and AFC are synchronized to CLKC. Tables

5 and 6 show the relationship of each port flag to FIFO1 and FIFO2.

EMPTY FLAGS (EFA, EFB)

The empty flag of a FIFO is synchronized to the Port Clock that reads

data from its array. When the empty flag is HIGH, new data can be read

to the FIFO output register. When the empty flag is LOW, the FIFO is

empty and attempted FIFO reads are ignored. When reading FIFO1 with

a byte or word size on Port B, EFB is set LOW when the fourth byte or

second word of the last long word is read.

The read pointer of a FIFO is incremented each time a new word is

clocked to the output register. The state machine that controls an empty

flag monitors a write-pointer and read-pointer comparator that indicates when

the FIFO SRAM status is empty, empty+1, or empty+2. A word written to a FIFO

can be read to the FIFO output register in a minimum of three cycles of the empty

flag synchronizing clock. Therefore, an empty flag is LOW if a word in memory

is the next data to be sent to the FIFO output register and two cycles of the Port

Clock that reads data from the FIFO have not elapsed since the time the word

was written. The empty flag of the FIFO is set HIGH by the second LOW-to-

HIGH transition of the synchronizing clock, and the new data word can be read

to the FIFO output register in the following cycle.

A LOW-to-HIGH transition on an empty flag synchronizing clock begins the

first synchronization cycle of a write if the clock transition occurs at time t

SKEW1

or greater after the write. Otherwise, the subsequent clock cycle can be the

first synchronization cycle (see Figure 12 and 13).

FULL FLAG (FFA, FFC)

The full flag of a FIFO is synchronized to the Port Clock that writes data to

its array. When the full flag is HIGH, a memory location is free in the SRAM

to receive new data. No memory locations are free when the full flag is LOW

and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, the write pointer is incremented.

The state machine that controls a full flag monitors a write-pointer and

read-pointer comparator that indicates when the FIFO SRAM status is full, full-

1, or full-2. From the time a word is read from a FIFO, the previous memory

location is ready to be written in a minimum of three cycles of the full flag

synchronizing clock. Therefore, a full flag is LOW if less than two cycles of the

full flag synchronizing clock have elapsed since the next memory write location

has been read. The second LOW-to-HIGH transition on the full flag synchro-

nization clock after the read sets the full flag HIGH and the data can be written

in the following clock cycle.

A LOW-to-HIGH transition on a full flag synchronizing clock begins the first

synchronization cycle of a read if the clock transition occurs at time t

SKEW1 or

greater after the read. Otherwise, the subsequent clock cycle can be the first

synchronization cycle (see Figure 14 and 15).

ALMOST-EMPTY FLAGS (AEA, AEB)

The Almost-Empty flag of a FIFO is synchronized to the Port Clock that reads

data from its array. The state machine that controls an Almost-Empty flag

monitors a write-pointer and a read-pointer comparator that indicates when

the FIFO SRAM status is almost-empty, almost-empty+1, or almost-empty+2.

The almost-empty state is defined by the value of the Almost-Full and Almost-

Empty Offset register (X). This register is loaded with one of four preset values

during a device reset (see Reset above). An Almost-Empty flag is LOW when

the FIFO contains X or less long words in memory and is HIGH when the FIFO

contains (X+1) or more long words.

Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock

are required after a FIFO write for the Almost-Empty flag to reflect the new level

of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1) or more

long words remains LOW if two cycles of the synchronizing clock have not

elapsed since the write that filled the memory to the (X+1) level. An Almost-

Empty flag is set HIGH by the second LOW-to-HIGH transition of the

synchronizing clock after the FIFO write that fills memory to the (X+1) level.

A LOW-to-HIGH transition of an Almost-Empty flag synchronizing clock begins

the first synchronization cycle if it occurs at time tSKEW2 or greater after the

write that fills the FIFO to (X+1) long words. Otherwise, the subsequent

synchronizing clock cycle can be the first synchronization cycle (see Figure

16 and 17).

ALMOST-FULL FLAGS (AFA, AFC)

The Almost-Full flag of a FIFO is synchronized to the Port Clock that writes

data to its array. The state machine that controls an Almost-Full flag monitors

a write-pointer and read-pointer comparator that indicates when the FIFO

SRAM status is almost-full, almost-full-1, or almost-full-2. The almost-full state

is defined by the value of the Almost-Full and Almost-Empty Offset register (X).

NOTE:

1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.

TABLE 5 — FIFO1 FLAG OPERATION

TABLE 6 — FIFO2 FLAG OPERATION

Synchronized Synchronized

Number of 36-Bit to CLKA to CLKC

Words in the FIFO2

EFA AEA AFC FFC

0LLHH

1 to X H L H H

(X+1) to [64–(X+1)] H H H H

(64–X) to 63 H H L H

64 H H L L

Synchronized Synchronized

Number of 36-Bit to CLKB to CLKA

Words in the FIFO1

(1)

EFB AEB AFA FFA

0LLHH

1 to X H L H H

(X+1) to [64–(X+1)] H H H H

(64–X) to 63 H H L H

64 H H L L

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723616 CMOS TRIPLE BUS SyncFIFO

™™

™ WITH

BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

This register is loaded with one of four preset values during a device reset (see

Reset above). An Almost-Full flag is LOW when the FIFO contains (64-X) or

more long words in memory and is HIGH when the FIFO contains [64-(X+1)]

or less long words.

Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock

are required after a FIFO read for the Almost-Full flag to reflect the new level

of fill. Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)] or less

words remains LOW if two cycles of the synchronizing clock have not elapsed

since the read that reduced the number of long words in memory to [64-(X+1)].

An Almost-Full flag is set HIGH by the second LOW-to-HIGH transition of the

synchronizing clock after the FIFO read that reduces the number of long words

in memory to [64-(X+1)]. A LOW-to-HIGH transition of an Almost-Full flag

synchronizing clock begins the first synchronization cycle if it occurs at time

tSKEW2 or greater after the read that reduces the number of long words in

memory to [64-(X+1)]. Otherwise, the subsequent synchronizing clock cycle

can be the first synchronization cycle (see Figure 18 and 19).

BUS SIZING

Both ports B and C, taken together, may be configured for either an 18-

bit word or a 9-bit byte format, thus determining the word width of the data

read from FIFO1 or written to FIFO2. Whichever bus size is selected

applies to both ports B and C. It is not possible to configure the bus width of ports

B and C independently.

The levels applied to the bus size select (SIZ0, SIZ1) inputs must be static

through out FIFO operation. These levels can only be changed when the FIFO

is idle (no read or write activity) just preceding Master Reset operation. The

bus size as selected using SIZ0 and SIZ1 is implemented according to Figure

2. Note that neither a HIGH nor a LOW logic level should be applied to both

SIZ0 and SIZ1 at the same time; these states are reserved.

Only 36-bit long-word data is written to or read from the two FIFO memories

on the IDT723616. Bus-matching operations are done after data is read from

the FIFO1 RAM and before data is written to the FIFO2 RAM.

BUS-MATCHING FIFO1 READS

Data is read from the FIFO1 RAM in 36-bit long word increments. Since

Port B can only have a byte or word size, only the first one or two bytes

appear on the selected portion of the FIFO1 output register, with the rest

of the long word stored in auxiliary registers. In this case, subsequent

FIFO1 reads with the same bus size implementation output the rest of the

long word to the FIFO1 output register in the order shown by Figure 2.

When reading data from FIFO1 in byte format, the unused B0-B17

outputs remain inactive but static, with the unused FIFO1 output register

bits holding the last data value to decrease power consumption.

BUS-MATCHING FIFO2 WRITES

Data is written to the FIFO2 RAM in 36-bit long word increments. Data

can be written to FIFO2 with a byte or word bus size. This action stores the

initial bytes or words in auxiliary registers. The CLKC rising edge that

writes the fourth byte or the second word of long word to FIFO2 also stores

the entire long word in FIFO2 RAM. The bytes are arranged in the manner

shown in Figure 2.

BYTE SWAPPING

The byte-order arrangement of data read from FIFO1 or data written to

FIFO2 can be changed synchronous to the rising edge of CLKB. Four

modes of byte-order swapping (including no swap) can be done with any

data port size selection. The order of the bytes are rearranged within the long

word, but the bit order within the bytes remains constant.

The swap configuration can be selected independently for ports B and C.

The Port B Swap Select inputs (SWB0 and SWB1) are used to choose the byte

arrangement for Port B. The Port C Swap Select inputs (SWC0 and SWC1)

are used to choose the byte arrangement for Port C. The levels applied to the

swap select must be static throughout FIFO operation. These levels can only

be changed when the FIFO is idle (no read or write activity) just preceding

Master Reset operation. Figures 3 and 4 are examples of the byte-order

swapping operations available for 18-bit words. Performing a byte swap and

bus size simultaneously for a FIFO1 read first rearranges the bytes as shown

in Figure 3, then outputs the bytes as shown in Figure 2. Simultaneous bus

sizing and byte swapping operations for FIFO2 writes first loads the data

according to Figure 2, then swaps the bytes as shown in Figure 4 when the

long word is loaded to FIFO2 RAM.

PARITY CHECKING

The Port A inputs (A0-A35) have four parity trees to check the parity of

incoming (or outgoing) data; the Port B inputs (B0-B17) have two parity trees

to check the parity of outgoing data; Port C inputs (C0-C17) have two parity

trees to check the parity of incoming data. A parity failure on one or more bytes

of the Port A data bus is reported by a LOW level on the port parity error flag

(PEFA). A parity failure on one or more bytes of the Port C data bus that are

valid for the bus size implementation is reported by a LOW level on the Port

C parity error flag (PEFC). Odd or even parity checking can be selected, and

the parity error flags can be ignored if this feature is not desired.

Parity status is checked on each input bus according to the level of the ODD/

EVEN parity select input. A parity error on one or more valid bytes of a port

is reported by a LOW level on the corresponding port parity error flag (PEFA,

PEFC) output. Port A bytes are arranged as A0-A8, A9-A17, A18-A26, and

A27-A35. Port C bytes are arranged as C0-C8 and C9-C17, and its valid bytes

are those used in a Port C bus size implementation. When ODD/EVEN parity

is selected, a port parity error flag (PEFA, PEFC) is LOW if any byte on the

port has an ODD/EVEN number of LOW levels applied to the bits.

PARITY GENERATION

A HIGH level on the Port A parity generate select (PGA) or Port B parity

generate select (PGB) enables the IDT723616 to generate parity bits for port

reads from a FIFO. Port A bytes are arranged as A0-A8, A9-A17, A18-26,

and A27-A35, with the most significant bit of each byte used as the parity bit.

Port B bytes are arranged as B0-B8 and B9-B17, with the most significant bit

of each byte used as the parity bit. A write to a FIFO stores the levels applied

to all nine inputs of a byte regardless of the state of the parity generate select

(PGA, PGB) inputs. When data is read from a port with parity generation

selected, the lower eight bits of each byte are used to generate a parity bit

according to the level on the ODD/EVEN select. The generated parity bits are

substituted for the levels originally written to the most significant bits of each byte

as the word is read to the data outputs.

Parity bits for FIFO data are generated after the data is read from SRAM

and before the data is written to the output register. Therefore, the Port A parity

generate select (PGA) and ODD/EVEN parity select (ODD/EVEN) have setup

and hold time constraints to the Port A clock (CLKA) and the Port B parity

generate select (PGB) and ODD/EVEN have setup and hold-time constraints

to the Port B clock (CLKB). These timing constraints only apply for a rising clock

edge used to read a new long word to the FIFO output register.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

723616L15PFG

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Description:

FIFO 64 X 36 X 2 FIFO

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