OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

723616L15PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
™™
™™
™ WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
010203040506070
0
50
100
150
200
250
300
350
400
⎯ Clock Frequency ⎯ MHz
fs
I
CC(f)
Supply Current mA
f data
= 1/2
f
s
T
A
= 25
°
C
C
L
= 0 pF
3520 drw04
80
V
CC
= 5.5V
V
CC
= 5V
V
CC
= 4.5V
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723616 with CLKA and CLKB set to
fs. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize
the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation
below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT723616 can be calculated by:
PT = VCC x ICC(f) + Σ(CL x VOH
2
x fo)
where:
CL = output capacitance load
fo = switching frequency of an output
VOH = output high level voltage
When no reads or writes are occurring on the IDT723616, the power dissipated by a single clock (CLKA or CLKB) input running at frequency
fS is calculated by:
PT=VCC x fS x 0.290 mA/MHz
Figure 1. Typical Characteristics: Supply Current vs Clock Frequency
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
™™
™™
™ WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
Commercial Com’l & Ind’l
(1)
IDT723616L15 IDT723616L20
Symbol Parameter Min. Max. Min. Max. Unit
fS Clock Frequency, CLKA, CLKB, or CLKC – 66.7 – 50 MHz
tCLK Clock Cycle Time, CLKA, CLKB, or CLKC 15 – 20 – ns
tCLKH Pulse Duration, CLKA, CLKB, and CLKC 6 – 8 – ns
tCLKL Pulse Duration, CLKA, CLKB, and CLKC 6 – 8 – ns
tDS Setup Time, A0-A35 before CLKA↑ and C0-C17 before CLKC↑ 4–5–ns
tENS Setup Time, CSA, W/RA, and ENA before CLKA↑; RENB before CLKB↑; 5–5–ns
WENC before CLKC↑
tSZS Setup Time, SIZ0 and SIZ1 before CLKB↑ and CLKC↑ 4–5–ns
tSWS Setup Time, SWB0 and SWB1 before CLKB↑, SWCO and SWC1, before CLKC↑ 5–7–ns
tPGS Setup Time, ODD/EVEN and PGA before CLKA↑; ODD/EVEN and PGB before 4 – 5 – ns
CLKB↑
(2)
tRSTS Setup Time, RST LOW before CLKA↑, CLKB↑, or CLKC↑
(3)
5–6–ns
tFSS Setup Time, FS0 and FS1 before RST HIGH 5 – 6 – ns
tDH Hold Time, A0-A35 after CLKA↑ and C0-C17 after CLKC↑ 1–1–ns
tENH Hold Time, CSA, W/RA, and ENA after CLKA↑; RENB after CLKB↑; WENB 1 – 1 – ns
after CLKC↑
tSZH Hold Time, SIZ0 and SIZ1 after CLKB↑ and CLKC↑ 2–2–ns
tSWH Hold Time, SWB0 and SWB1 after CLKB↑, SWC0 and SWC1 after CLKC↑ 0–0–ns
tPGH Hold Time, ODD/EVEN and PGA after CLKA↑; ODD/EVEN and PGB after 0 – 0 – ns
CLKB↑
(2)
tRSTH Hold Time, RST LOW after CLKA↑, CLKB↑ or CLKC↑
(2)
5–6–ns
tFSH Hold Time, FS0 and FS1 after RST HIGH 4 – 4 – ns
tSKEW1
(4)
Skew Time, between CLKA↑ and CLKB↑ for EFB and FFA; between CLKC↑ 8–8–ns
and CLKA↑ for EFA and FFC
tSKEW2
(4)
Skew Time, between CLKA↑ and CLKB↑ for AEB and AFA; between CLKC↑ 14 – 16 – ns
and CLKA↑ for AEA and AFC
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Only applies for a clock edge that does a FIFO read.
3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationships among CLKA cycle, CLKB cycle and CLKC.
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
™™
™™
™ WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
Commercial Com’l & Ind’l
(1)
IDT723616L15 IDT723616L20
Symbol Parameter Min. Max. Min. Max. Unit
tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B17 2 10 2 12 ns
tWFF Propagation Delay Time, CLKA↑ to FFA and CLKC↑ to FFC 210212ns
tREF Propagation Delay Time, CLKA↑ to EFA and CLKB↑ to EFB 210212ns
tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 210212ns
tPAF Propagation Delay Time, CLKA↑ to AFA and CLKC↑ to AFC 210212ns
tPPE
(2)
Propagation delay time, CLKB↑ to PEFB 210212ns
t
PDPE Propagation Delay Time, A0-A35 valid to PEFA valid; C0-C17 valid to PEFC 210211ns
valid
tPOPE Propagation Delay Time, ODD/EVEN to PEFA and PEFC 210212ns
tPEPE Propagation Delay Time, W/RA or PGA to PEFA 110112ns
tEN Enable Time, CSA and W/RA LOW to A0-A35 active and RENB HIGH to B0-B17 2 10 2 12 ns
active
tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and RENB LOW 1 8 1 9 ns
to B0-B17 at high-impedance
NOTE:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Only applies when a new port B bus size is implemented by the rising CLKB edge.
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

723616L15PFG

Mfr. #:
Buy 723616L15PFG
Manufacturer:
IDT
Description:
FIFO 64 X 36 X 2 FIFO
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet