3
COMMERCIAL TEMPERATURE RANGE
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36, 1,024 x 36
to the LOW-to-HIGH transition of a port clock by enable signals. The
clocks for each port are independent of one another and can be
asynchronous or coincident. The enables for each port are arranged to
provide a simple bidirectional interface between microprocessors and/or
buses with synchronous control.
Communication between each port may bypass the FIFO via two
mailbox registers. The mailbox registers' width matches the selected Port
B bus width. Each mailbox register has a flag (MBF1 and MBF2) to signal
when new mail has been stored.
Two kinds of reset are available on these FIFOs: Reset and Partial Reset.
Reset initializes the read and write pointers to the first location of the memory array
and selects serial flag programming, parallel flag programming, or one of three
possible default flag offset settings, 8, 16 or 64.
Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,
programming method and partial flag default offsets) are retained. Partial Reset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
word written to an empty FIFO appears automatically on the outputs, no read
operation required (Nevertheless, accessing subsequent words does neces-
sitate a formal read request). The state of the BE/FWFT pin during Reset
determines the mode in use.
The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a
combined Full/Input Ready Flag (FF/IR). The EF and FF functions are selected
in the IDT Standard mode. EF indicates whether or not the FIFO memory is
empty. FF shows whether the memory is full or not. The IR and OR
functions are selected in the First Word Fall Through mode. IR indicates
whether or not the FIFO has available memory locations. OR shows
whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
The FIFO has a programmable Almost-Empty flag (AE) and a
programmable Almost-Full flag (AF). AE indicates when a selected
number of words remain in the FIFO memory. AF indicates when the
FIFO contains more than a selected number of words.
FF/IR and AF are two-stage synchronized to the port clock that writes data
into its array. EF/OR and AE are two-stage synchronized to the port clock that
reads data from its array. Programmable offsets for AE and AF are loaded in
parallel using Port A or in serial via the SD input. The Serial Programming Mode
pin (SPM) makes this selection. Three default offset settings are also provided.
The AE threshold can be set at 8, 16 or 64 locations from the empty boundary
and the AF threshold can be set at 8, 16 or 64 locations from the full boundary.
All these choices are made using the FS0 and FS1 inputs during Reset.
Two or more devices may be used in parallel to create wider data paths.
In First Word Fall Through mode, more than one device may be connected in
series to create greater word depths. The addition of external components is
unnecessary.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (I
CC) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the Power Down state.
The IDT72V3623/72V3643 are characterized for operation from 0°C
to 70°C. Industrial temperature range (-40°C to +85°C) is available by
special order. They are fabricated using high speed, submicron CMOS
technology.
