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72V3623L10PFG
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P28
16
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
NOTES:
1.
RS1
must be HIGH during Partial Reset.
2
. If BE/
FWFT
is HIGH, then
EF
/OR will go LOW one CLKB cycle earlier than in this case where BE/
FWFT
is LOW.
Figure 4. Partial Reset (IDT Standard and FWFT Modes)
NOTES:
1.
PRS
must be HIGH during Reset.
2
. If BE/
FWFT
is HIGH, then
EF
/OR will go LOW one CLKB cycle earlier than in this case where BE/
FWFT
is LOW.
Figure 3. Reset and Loading X and Y with a Preset Value of Eight (IDT Standard and FWFT Modes)
t
RSF
CLKA
RS1
,
RS2
FF
/IR
AE
AF
MBF1
,
MBF2
CLKB
EF
/OR
FS1,FS0
4662 drw 05
t
RSTS
t
RSTH
t
FSH
t
FSS
t
WFF
t
REF
(2)
t
RSF
0,1
t
RSF
BE
BE/
FWFT
SPM
FWFT
t
BES
t
SPMS
t
SPMH
1
2
t
FWS
t
BEH
t
WFF
CLKA
PRS
FF
/IR
AE
AF
MBF1
,
CLKB
EF
/OR
4662 drw 06
t
RSTS
t
RSTH
t
WFF
t
WFF
t
REF
t
RSF
t
RSF
t
RSF
MBF2
(2)
17
COMMERCIAL TEMPERATURE RANGE
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36, 1,024 x 36
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Mod
es)
NOTE:
1.
CSA
= LOW, W/
R
A = HIGH, MBA = LOW.
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT
Modes)
NOTES:
1
. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until
FF
/IR is set HIGH.
2
.
Programmable offsets are written serially to the SD input in the order
AF
offset (Y) and
AE
offset (X).
4662 drw 07
CLKA
RS1
FF
/IR
A0-A35
FS1,FS0
ENA
t
FSH
t
WFF
t
ENH
t
ENS2
t
DS
t
DH
4
0,0
AF
Offset
(
Y
)
AE
Offset
(X)
First Word to FIFO1
t
FSH
t
FSS
SPM
t
FSS
1
2
CLKA
FF
/IR
t
SENS
t
SENH
FS0/SD
(2)
t
SPH
t
SENS
t
SENH
t
FSS
t
WFF
FS1/
SEN
AE
Offset
(
X
)
LSB
t
SDS
t
SDH
t
SDS
t
SDH
AF
Offset
(
Y
)
MSB
RS1
4
t
FSS
t
FSH
SPM
4662 drw 08
18
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
NOTE:
1.
Data read from the FIFO
NOTE:
1.
BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 8. Port B Long-Word Read Cycle (IDT Standard and FWFT Modes)
SIZE MODE
(1)
DATA WRITTEN TO FIFO
DATA
READ
FROM
FIFO
(SELECT AT RESET)
B
M
SIZE
B
E
A35-A27
A26-A18
A17-A9
A8-A0
B35-B27
B26-B18
B17-B9
B8-B0
LX
X
A
B
C
D
A
B
C
D
D
A
T
A SIZE T
ABLE FOR FIFO LONG-WORD READS
NOTE:
1.
Written to FIFO.
Figure 7. Port A Write Cycle Timing for FIFO (IDT Standard and FWFT Modes)
4662 drw09
CLKA
FF
/IRA
ENA
A0-A35
MBA
CSA
W/
R
A
t
CLKH
t
CLKL
t
CLK
t
ENS1
t
DS
t
ENH
t
ENH
t
ENH
t
ENH
t
DH
W1
(1)
W2
(1)
t
ENH
t
ENH
No Operation
HIGH
t
ENS2
t
ENS2
t
ENS2
t
ENS2
t
ENS2
4662 drw 10
CLKB
EF
/OR
ENB
MBB
CSB
W
/RB
t
DIS
t
CLK
t
CLKH
t
CLKL
t
A
t
MDV
t
EN
t
A
t
ENH
t
ENH
W1
(1)
W2
(1)
W3
(1)
t
ENH
t
DIS
t
EN
W2
(1)
(1)
W1
Previous Data
t
MDV
t
A
OR
B0-B35
(Standard Mode)
B0-B35
(FWFT Mode)
t
A
No Operation
HIGH
t
ENS2
t
ENS2
t
ENS2
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P28
72V3623L10PFG
Mfr. #:
Buy 72V3623L10PFG
Manufacturer:
IDT
Description:
FIFO 8KX36K2 BUS BIDIRECTIONAL
Lifecycle:
New from this manufacturer.
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