Figure 9. Port B Word Read Cycle Timing (IDT Standard and FWFT Modes)
NOTE:
1.BE is selected at Reset: BM and SIZE must be static throughout device operation.
NOTE:
1.Unused word B18-B35 are indeterminate.
CLKB
ENB
FF/OR
W/RB
CSB
HIGH
4662 drw 11
B0-B17
Previous Data
t
DIS
t
A
t
A
t
ENH
No Operation
Read 1
B0-B17
t
A
t
A
Read 1
Read 2
Read 2
Read 3
t
DIS
MBB
(Standard Mode)
(FWFT Mode)
OR
t
EN
t
MDV
t
MDV
t
EN
t
ENS2
20
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
BMSIZEBEA35-A27A26-A18A17-A9A8-A0B8-B0
HHHABCD
HHLABCD
1 D
2 C
3 B
4 A
Figure 10. Port B Byte Read Cycle Timing (IDT Standard and FWFT Modes)
NOTE:
1.BE is selected at Reset: BM and SIZE must be static throughout device operation.
SIZE MODE
(1)
DATA WRITTEN TO FIFOREADDATA READ FROM FIFO
NO.
NOTE:
1.Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate.
1 A
2 B
3 C
4 D
DATA SIZE TABLE FOR BYTE READS
EF/OR
MBB
CSB
W/RB
ENB
CLKB
4662 drw 12
HIGH
B0-B8
B0-B8
Read 5
Read 2Read 3
Read 4
Read 1
Read 4
Previous DataRead 2
No Operation
tDIS
tDIS
tA
tA
tA
tA
tA
tA
tENH
tA
tA
Read 1
(Standard Mode)
(FWFT Mode)
tEN
tMDV
tMDV
tEN
OR
Read 3
tENS2
21
COMMERCIAL TEMPERATURE RANGE
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36, 1,024 x 36
NOTES:
1.tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB cycles. If the time
between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load of the first word to the output register may occur one CLKB cycle later than shown.
2.If Port B size is word or byte, OR is set LOW by the last word or byte read from the FIFO, respectively.
Figure 11. OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)
