25
COMMERCIAL TEMPERATURE RANGE
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36, 1,024 x 36
Figure 17. Timing for Mail1 Register and
MBF1MBF1
MBF1MBF1
MBF1
Flag (IDT Standard and FWFT Modes)
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 Register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35 will
be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8
(A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B35 will be indeterminate).
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge
is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3623, 1,024 for the IDT72V3643.
4. If Port B size is word or byte, t
SKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 16. Timing for
AFAF
AFAF
AF
when the FIFO is Almost-Full (IDT Standard and FWFT Modes).
AF
CLKA
ENB
4662 drw 18
ENA
CLKB
12
t
SKEW2
t
ENH
t
PAF
t
ENH
t
PAF
[D-(Y+1)] Words in FIFO
(D-Y) Words in FIFO
(1)
t
ENS2
t
ENS2
4662 drw19
CLKA
ENA
A0-A35
MBA
CSA
W/RA
CLKB
MBF1
CSB
MBB
ENB
B0-B35
W/RB
t
ENH
t
DS
t
DH
t
PMF
t
PMF
t
ENH
t
DIS
t
EN
t
MDV
t
PMR
FIFO Output Register W1 (Remains valid in Mail1 Register after read)
t
ENH
t
ENH
t
ENH
W1
t
ENS1
t
ENS2
t
ENS2
t
ENS2
t
ENS2
