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NCL30186BDR2G

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NCL30186
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19
Application Information
The NCL30186 is a driver for power−factor corrected
flyback and non−isolated buck−boost/ SEPIC converters. It
implements a current−mode, quasi−resonant architecture
including valley lockout and frequency fold−back
capabilities for maintaining high−efficiency performance
over a wide load range. A proprietary circuitry ensures both
accurate regulation of the output current (without the need
for a secondary−side feedback) and near−unity power factor
correction. The circuit contains a suite of powerful
protections to ensure a robust LED driver design without the
need of extra external components or overdesign
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30186 optimizes the
efficiency by turning on the MOSFET when its
drain−source voltage is minimal (valley). In light−load
conditions, the circuit changes valleys to reduce the
switching losses. For a stable operation, the valley at
which the MOSFET switches on remains locked until
the input voltage or the output current set−point
significantly changes.
• Primary−Side Constant−Current Control with
Power Factor Correction: a proprietary circuitry
allows the LED driver to achieve both near−unity
power factor correction and accurate regulation of the
output current without requiring any secondary−side
feedback (no optocoupler needed). A power factor as
high as 0.99 and an output current deviation below ±2%
are typically obtained.
• Linear or PWM dimming: the DIM pin allows
implementing both analog and PWM dimming.
• Main protection features:
♦ Over Temperature Thermal Fold−back/
Shutdown/Over Voltage Protection: the
NCL30186 features a gradual current foldback to
protect the driver from excessive temperature down
to 50% of the programmed current. If the
temperature continues to rise after this point to a
second level, the controller stops operating. This
mode would only be expected to be reached under
normal conditions if there is a severe fault. The first
and second temperature thresholds depend on the
NTC connected to the circuit SD pin. The SD pin
can also be used to shutdown the device by pulling
this pin below the V
OTP(off)
min level. A Zener
diode can also be used to pull−up the pin and stop
the controller for adjustable OVP protection. Both
protections are latching−off (A and C versions) or
auto−recovery (the circuit can recover operation
after 4−s delay has elapsed − B and D versions).
♦ Cycle−by−cycle peak current limit: when the
current sense voltage exceeds the internal threshold
V
ILIM
, the MOSFET is immediately turned off.
♦ Winding or Output Diode Short−Circuit
Protection: an additional comparator senses the CS
signal and stops the controller if it exceeds 150% x
V
ILIM
for 4 consecutive cycles. This feature can
protect the converter if a winding is shorted or if the
output diode is shorted or simply if the transformer
saturates. This protection is latching−off (A and C
versions) or auto−recovery (B and D versions).
♦ Output Short−circuit protection: if the ZCD pin
voltage remains low for a 90−ms time interval, the
controller detects that the output or the ZCD pin is
grounded and hence, stops operation. This protection
is latching−off (A and C versions) or auto−recovery
(B and D versions).
♦ Open LED protection: if the V
CC
pin voltage
exceeds the OVP threshold, the controller shuts
down and waits 4 seconds before restarting
switching operation.
♦ Floating or Short Pin Detection: NCL30186
protections aid in pass safety tests. For instance, the
circuit stops operating when the CS pin is grounded
or open.
Power Factor and Constant Current Control
The NCL30186 embeds an analog/digital block to control
the power factor and regulate the output current by
monitoring the ZCD, V
S
and CS pin voltages (signals ZCD,
V
S
and V
CS
of Figure 59). This circuitry generates the
current setpoint (V
CONTROL
/4) and compares it to the
current sense signal (V
CS
) to dictate the MOSFET turning
off event when V
CS
exceeds V
CONTROL
/4.
Power Factor and
Constant−Current
Control
PWM Latch reset
STOP
V
VS
REF
V
COMP
ZCD
C1
CS
V
DIM_disable
Figure 59. Power Factor and Constant−Current Control
NCL30186
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20
The V
S
pin provides the sinusoidal reference necessary
for shaping the input current. The obtained current reference
is further modulated so that when averaged over a half−line
period, it is equal to the output current reference (V
REFX
).
This averaging process is made by an internal Operational
Trans−conductance Amplifier (OTA) and the capacitor
connected to the COMP pin (C1 in Figure 59). Typical
COMP capacitance is 2.2 mF and should not be less than 1 mF
to ensure stability. The COMP ripple does not affect the
power factor performance as the circuit digitally eliminates
it when generating the current setpoint.
If the V
S
pin properly conveys the sinusoidal shape, power
factor will be close to 1. Also, the Total Harmonic Distortion
(THD) will be low, especially if the output voltage ripple is
small. In any case, the output current will be well regulated
following the equation below:
I
out
+
V
REFX
2N
PS
R
sense
(eq. 1)
Where:
• N
PS
is the secondary to primary transformer turns N
PS
= N
S
/ N
P
• R
sense
is the current sense resistor (see Figure 1).
• V
REFX
is the output current internal reference. V
REFX
=
V
REF
(250 mV in A and B versions and 200 mV in C
and D versions, typically) at full load.
The output current reference (V
REFX
) is V
REF
unless
thermal fold−back is activated by the SD pin voltage being
reduced below 1 V typical (see “protections” section) or
unless the DIM pin voltage is below V
DIM100
(see analog
dimming section).
If a major fault is detected, the circuit enters the
latched−off or auto−recovery mode and the COMP pin is
grounded (except in an UVLO condition). This ensures a
clean start−up when the circuit resumes operation.
Start−up Sequence
Generally an LED lamp is expected to emit light in < 1 sec
and typically within 300 ms. The start−up phase consists of
the time to charge the V
CC
capacitor, initiate startup and
begin switching and the time to charge the output capacitor
until sufficient current flows into the LED string. To
speed−up this phase, the following defines the start−up
sequence:
• The COMP pin is grounded when the circuit is off. The
average COMP voltage needs to exceed the V
S
pin
peak value to have the LED current properly regulated
(whatever the current target is). To speed−up the COMP
capacitance charge and shorten the start−up phase, an
internal 80−mA current source adds to the OTA sourced
current (60 mA max typically) to charge up the COMP
capacitance. The 80−mA current source remains on until
the OTA starts to sink current as a result of the COMP
pin voltage sufficient rise. At that moment, the COMP
pin being near its steady−state value, it is only driven
by the OTA.
• If V
CC
drops below the V
CC(off)
threshold because the
circuit fails to start−up properly on the first attempt, a
new attempt takes place as soon as V
CC
is recharged to
V
CC(on)
. The COMP voltage is not reset at that
moment. Instead, the new attempt starts with the
COMP level obtained at the end of the previous
operating phase.
• If the load is shorted, the circuit will operate in hiccup
mode with V
CC
oscillating between V
CC(off)
and
V
CC(on)
until the AUX_SCP protection trips
(AUX_SCP is triggered if the ZCD pin voltage does
not exceed 1 V within a 90−ms operation period of time
thus indicating a short to ground of the ZCD pin or an
excessive load preventing the output voltage from
rising). The NCL30186A and NCL3006C latch off in
this case. With the B and D versions, the AUX_SCP
protection forces the 4−s auto−recovery delay to reduce
the operation duty−ratio. Figure 60 illustrates a start−up
sequence with the output shorted to ground, in this
second case.
NCL30186
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21
CC(on)
V
CC(off)
V
()
4
recovery
ts^
()
‧‧‧
1
t
2
t
3
t
()
12 3
90
OVLD
OVLD
AUX_SCPtrips
as t t t
tms
+
^
1
t
2
t
3
t
()
4
recovery
ts^
()
‧‧‧
CC
V
DRV
time
time
Figure 60. Start−up Sequence in a Load Short−circuit Situation (auto−recovery versions)
t +=
Zero Crossing Detection Block
The ZCD pin detects when the drain−source voltage of the
power MOSFET reaches a valley by crossing below the
55−mV internal threshold (V
ZCD(TH)
). At startup or in case
of extremely damped free oscillations, the ZCD comparator
may not be able to detect the valleys. To avoid such a
situation, the NCL30186 features a time−out circuit that
generates pulses if the voltage on ZCD pin stays below the
55−mV threshold for 6.5 ms nominal. The time−out also acts
as a substitute clock for the valley detection and simulates
a missing valley in case the free oscillations are too damped.
Figure 61. Zero Current Detection Block
+
−
ZCD
V
ZCD(TH)
Time−Out
Clock
+
−
V
ZCD(short)
+
−
S
R
Q
Q
Aux_SCP
90−ms Timer
4−s Timer (auto−recovery version)
FF_mode
t
ZCD(blank2)
t
ZCD(blank1)
t
ZCD(blank)
Vcc<Vcc(reset) (latching−off version)
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NCL30186BDR2G

Mfr. #:
Buy NCL30186BDR2G
Manufacturer:
ON Semiconductor
Description:
AC/DC Converters LED LIGHTING CONTROLLER
Lifecycle:
New from this manufacturer.
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