NCL30186
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4
Internal Circuit Architecture
SD
Thermal
Foldback
Over Temp. Protection
Over Voltage Protection
ZCD
Zero Crossing Detection Logic
(ZCD Blanking, Time−Out, ...)
Valley Selection
CS
Power Factor and
Constant−Current
Control
Leading
Edge
Blanking
Winding and
Output diode
Short Circuit
Protection
Max. Peak
Current
Limit
Ipkmax
WOD_SCP
DRV
VCC Management
VCC
DRV
VCC Over Voltage
Protection
VCC
Internal
Thermal
Shutdown
(Auto−recovery or Latched)
Fault
Management
Clamp
Circuit
VS
Brown−Out
BO_NOK
S
R
Q
Q
CS_reset
STOP
UVLO
OFF
Latch
STOP
WOD_SCP
BO_NOK
GND
STOP
Aux. Winding Short Circuit Prot.
Aux_SCP
Aux_SCP
VCC_max
FF_mode
V
Line
feed−forward
VS
V
VS
Ipkmax
V
TF
V
REF
V
DD
V
REF
V
VS
Enable
CS Short
Protection
CS_ok
CS_ok
Frequency Foldback
FF_mode
Maximum
on time
UVLO
on,max
t
on,max
t
V
VS
COMP
V
REFX
DIM
Dimming
control
DIM_disable
V
REFX
TF
V
DIM_disable
DIM_disable
Figure 3. Internal Circuit Architecture
(Auto−recovery or Latched)
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5
Table 3. MAXIMUM RATINGS TABLE(S)
Symbol Rating Value Unit
V
CC(MAX)
I
CC(MAX)
Maximum Power Supply voltage, V
CC
pin, continuous voltage
Maximum current for V
CC
pin
−0.3 to 30
Internally limited
V
mA
V
DRV(MAX)
I
DRV(MAX)
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, V
DRV
(Note 1)
−300, +500
V
mA
V
MAX
I
MAX
Maximum voltage on low power pins (except DRV and V
CC
pins)
Current range for low power pins (except DRV and V
CC
pins)
−0.3, 5.5 (Notes 2 and 5)
−2, +5
V
mA
R
θ
J−A
Thermal Resistance Junction−to−Air 180 °C/W
T
J(MAX)
Maximum Junction Temperature 150 °C
Operating Temperature Range −40 to +125 °C
Storage Temperature Range −60 to +150 °C
ESD Capability, HBM model (Note 3) 3.5 kV
ESD Capability, MM model (Note 3) 250 V
ESD Capability, CDM model (Note 3) 2 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
DRV
is the DRV clamp voltage V
DRV(high)
when V
CC
is higher than V
DRV(high)
. V
DRV
is V
CC
otherwise.
2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5−V Zener diode. More positive and negative voltages can
be applied if the pin current stays within the −2 mA / 5 mA range.
3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E,
Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E.
4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds ±100 mA.
5. Recommended maximum V
S
voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the V
S
pin recommended range.
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T
J
= 25°C, V
CC
= 12 V, V
ZCD
= 0 V,
V
CS
= 0 V, V
SD
= 1.5 V) For min/max values T
J
= −40°C to +125°C, V
CC
= 12 V)
Description
Test Condition Symbol Min Typ Max Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis V
CC(on)
– V
CC(off)
Internal logic reset
V
CC
rising
V
CC
rising
V
CC
falling
V
CC(on)
V
CC(off)
V
CC(HYS)
V
CC(reset)
16.0
8.2
8
4
18.0
8.8
5
20.0
9.4
6
V
V
CC
Over Voltage Protection Threshold V
CC(OVP)
25.5 26.8 28.5 V
V
CC(off)
noise filter
V
CC(reset)
noise filter
t
VCC(off)
t
VCC(reset)
5
20
ms
Startup current I
CC(start)
13 30
mA
Startup current in fault mode I
CC(Fault)
58 75
mA
Supply Current
Device Disabled/Fault
Device Enabled/No output load on DRV pin
Device Switching
V
CC
> V
CC(off)
F
sw
= 65 kHz
C
DRV
= 470 pF, F
sw
= 65 kHz
I
CC1
I
CC2
I
CC3
0.8
1.0
2.6
3.0
1.2
4.0
4.5
mA
CURRENT SENSE
Maximum Internal current limit
V
ILIM
0.95 1.00 1.05 V
Leading Edge Blanking Duration for V
ILIM
t
LEB
240 300 360 ns
Propagation delay from current detection to gate
off−state
t
ILIM
100 150 ns
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters R
TF(start)
, R
TF(stop)
, R
OTP(off)
and R
OTP(on)
give the resistance the
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V
CC
reaches V
CC(on)
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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6
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T
J
= 25°C, V
CC
= 12 V, V
ZCD
= 0 V,
V
CS
= 0 V, V
SD
= 1.5 V) For min/max values T
J
= −40°C to +125°C, V
CC
= 12 V)
Description UnitMaxTypMinSymbolTest Condition
CURRENT SENSE
Maximum on−time
t
on(MAX)
26 36 46
ms
Threshold for immediate fault protection activation V
CS(stop)
1.35 1.50 1.65 V
Leading Edge Blanking Duration for V
CS(stop)
t
BCS
150 ns
Current source for CS to GND short detection I
CS(short)
400 500 600
mA
Current sense threshold for CS to GND short de-
tection
V
CS
rising V
CS(low)
30 65 100 mV
GATE DRIVE
Drive Resistance
DRV Sink
DRV Source
R
SNK
R
SRC
13
30
W
Drive current capability
DRV Sink (Note 6)
DRV Source (Note 6)
I
SNK
I
SRC
500
300
mA
Rise Time (10% to 90%) C
DRV
= 470 pF t
r
40 ns
Fall Time (90% to 10%) C
DRV
= 470 pF t
f
30 ns
DRV Low Voltage V
CC
= V
CC(off)
+0.2 V
C
DRV
= 470 pF, R
DRV
= 33 kW
V
DRV(low)
8 V
DRV High Voltage V
CC
= V
CC(MAX)
C
DRV
= 470 pF, R
DRV
= 33 kW
V
DRV(high)
10 12 14 V
ZERO VOLTAGE DETECTION CIRCUIT
Upper ZCD threshold voltage
V
ZCD
rising V
ZCD(rising)
90 150 mV
Lower ZCD threshold voltage V
ZCD
falling V
ZCD(falling)
35 55 mV
ZCD hysteresis V
ZCD(HYS)
15 mV
Propagation Delay from valley detection to DRV
high
V
ZCD
falling T
DEM
100 300 ns
Blanking delay after on−time V
REFX
> 30% V
REF
T
ZCD(blank1)
1.12 1.50 1.88
ms
Blanking delay at light load V
REFX
< 25% V
REF
T
ZCD(blank2)
0.56 0.75 0.94
ms
Timeout after last DEMAG transition T
TIMO
5.0 6.5 8.0
ms
Pulling−down resistor V
ZCD
= V
ZCD(falling)
R
ZCD(PD)
200
kW
CONSTANT CURRENT AND POWER FACTOR CONTROL
Reference Voltage at T
J
= 25°C A and B versions
C and D versions
V
REF
245
195
250
200
255
205
mV
Reference Voltage T
J
= 25°C to 100°C A and B versions
C and D versions
V
REF
242.5
192.5
250.0
200.0
257.5
207.5
mV
Reference Voltage T
J
= −40°C to 125°C A and B versions
C and D versions
V
REF
240
190
250
200
260
210
mV
Current sense lower threshold V
CS
falling V
CS(low)
20 50 100 mV
V
control
to current setpoint division ratio V
ratio
4
Error amplifier gain V
REFX
= V
REF
G
EA
40 50 60
mS
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters R
TF(start)
, R
TF(stop)
, R
OTP(off)
and R
OTP(on)
give the resistance the
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V
CC
reaches V
CC(on)
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.

NCL30186BDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
AC/DC Converters LED LIGHTING CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
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