NCL30186
www.onsemi.com
24
Notes:
• The current does not immediately reach its new target
value when the PWM dimming signal state changes due
to system time constants like the time necessary to
charge or discharge the output capacitor to the required
level. The output current settling time can hence affect
the obtained output current, particularly if the PWM
signal frequency is high.
• If either the high−state (V
DIM(high)
) or low−state level
(V
DIM(low)
) of the input or both are between V
DIM0
and
V
DIM100
, the output current will be proportionally
reduced as both analog and PWM dimming are
simultaneous active, thus the output current will be:
I
out
^
ǒ
V
DIM(high)
* V
DIM0
V
DIM100
* V
DIM0
d )
V
DIM(low)
* V
DIM0
V
DIM100
* V
DIM0
(1 * d)
Ǔ
I
out,nom
if V
DIM0
v V
DIM(low)
v V
DIM(high)
v V
DIM100
I
out
^
V
DIM(high)
* V
DIM0
V
DIM100
* V
DIM0
d @ I
out,nom
if V
DIM0
v V
DIM(high)
v V
DIM100
and V
DIM(low)
v V
DIM0
I
out
^
ǒ
d )
V
DIM(low)
* V
DIM0
V
DIM100
* V
DIM0
(1 * d)
Ǔ
I
out,nom
if V
DIM(high)
w V
DIM100
and V
DIM0
v V
DIM(low)
v V
DIM100
• If thermal foldback is activated as well, the current
reduction is cumulative. For instance, if the DIM pin
voltage and the thermal foldback respectively, reduces
the output current setpoint by 50% and 20%
respectively, the output current will be 80%*50% that is
40% of its nominal level.
The DIM pin is pulled up internally by a 10−mA current source.
Thus, if the pin is let open, the controller is able to start.
For any power factor corrected single stage architecture
there will be a component of line ripple (100 / 120 Hz) on the
output. If PWM dimming is used, it is recommended to
select the dimming frequency to be sufficiently high not to
generating beat frequencies that could create optical
artifacts.
>> As a general rule, the minimum PWM frequency
should be at least 2.5x the line ripple frequency and not
be set near multiples of the line frequency.
Protections
The circuit incorporates a full suite of protection features
listed below to make the LED driver very rugged.
Output Short Circuit Situation
An overload fault is detected if the ZCD pin voltage
remains below V
ZCD(short)
for 90 ms. In such a situation, the
circuit stops generating pulses until the 4−s delay
auto−recovery time has elapsed (B and D versions) or
latches off (A and C versions).
Winding or Output Diode Short Circuit Protection
If a transformer winding happens to be shorted, the
primary inductance will collapse leading the current to ramp
up in a very abrupt manner. The V
ILIM
comparator (current
limitation threshold) will trip to open the MOSFET and
eventually stop the current rise. However, because of the
abnormally steep slope of the current, internal propagation
delays and the MOSFET turn−off time, a current rise > 50%
of the nominal maximum value set by V
ILIM
is possible. As
illustrated in Figure 66, an additional circuit monitors for
this current overshoot to detect a winding short circuit. The
leading edge blanking (LEB) time for short circuit
protection (LEB2) is significantly faster than the LEB time
for cycle−by−cycle protection (LEB1). Practically, if four
consecutive switching periods lead the CS pin voltage to
exceed (V
CS(stop)
= 150% * V
ILIM
), the controller enters the
auto−recovery mode (4−s operation interruption between
active bursts with versions B and D) or latches off (versions
A and C).
