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RF Input and Output Stage (ANTP/ANTN)
The AX8052F151 uses fully differential antenna pins.
RX/TX switching is handled internally. An external RX/TX
switch is not required.
LNA
The LNA amplifies the differential RF signal from the
antenna and buffers it to drive the I/Q mixer. An external
matching network is used to adapt the antenna impedance to
the IC impedance. A DC feed to the regulated supply voltage
VREG must be provided at the antenna pins. For
recommendations see section: Application Information.
I/Q Mixer
The RF signal from the LNA is mixed down to an IF of
typically 1 MHz. I and QIF signals are buffered for the
analog IF filter.
PA
In TX mode the PA drives the signal generated by the
frequency generation subsystem out to the differential
antenna terminals. The output power of the PA is
programmed via bits TXRNG[3:0] in the register
AX5051_TXPWR. Output power as well as harmonic
content will depend on the external impedance seen by the
PA, recommendations are given in the applications section.
Analog IF Filter
The mixer is followed by a complex bandpass IF filter,
which suppresses the downmixed image while the wanted
signal is amplified. The center frequency of the filter is
1 MHz, with a passband width of 1 MHz. The RF
frequency generation subsystem must be programmed in
such a way that for all possible modulation schemes the IF
frequency spectrum fits into the passband of the analog
filter.
Digital IF Channel Filter and Demodulator
The digital IF channel filter and the demodulator extract
the data bitstream from the incoming IF signal. They must
be programmed to match the modulation scheme as well as
the data rate. Inaccurate programming will lead to loss of
sensitivity.
The channel filter offers bandwidths of 40 kHz up to
600 kHz.
For detailed instructions how to program the digital
channel filter and the demodulator see the AX5051
Programming Manual, an overview of the registers involved
is given in the following table. The register setups typically
must be done once at powerup of the device.
Table 19. REGISTERS
Register Remarks
AX5051_CICDEC This register programs the bandwidth of the digital channel filter.
AX5051_DATARATEHI,
AX5051_DATARATELO
These registers specify the receiver bit rate, relative to the channel filter bandwidth.
AX5051_TMGGAINHI,
AX5051_TMGGAINLO
These registers specify the aggressiveness of the receiver bit timing recovery. More aggressive
settings allow the receiver to synchronize with shorter preambles, at the expense of more timing
jitter and thus a higher bit error rate at a given signaltonoise ratio.
AX5051_MODULATION This register selects the modulation to be used by the transmitter and the receiver, i.e. whether
ASK, PSK , FSK, MSK or OQPSK should be used.
AX5051_PHASEGAIN,
AX5051_FREQGAIN,
AX5051_FREQGAIN2,
AX5051_AMPLGAIN
These registers control the bandwidth of the phase, frequency offset and amplitude tracking loops.
Recommended settings are provided in the AX5051 Programming Manual.
AX5051_AGCATTACK,
AX5051_AGCDECAY
These registers control the AGC (automatic gain control) loop slopes, and thus the speed of gain
adjustments. The faster the bit rate, the faster the AGC loop should be. Recommended settings
are provided in the AX5051 Programming Manual.
AX5051_TXRATE These registers control the bit rate of the transmitter.
AX5051_FSKDEV These registers control the frequency deviation of the transmitter in FSK mode. The receiver does
not explicitly need to know the frequency deviation, only the channel filter bandwidth has to be set
wide enough for the complete modulation to pass.
Encoder
The encoder is located between the Framing Unit, the
Demodulator and the Modulator. It can optionally transform
the bitstream in the following ways:
It can invert the bit stream.
It can perform differential encoding. This means that a
zero is transmitted as no change in the level, and a one
is transmitted as a change in the level. Differential
encoding is useful for PSK, because PSK transmissions
can be received either as transmitted or inverted, due to
the uncertainty of the initial phase. Differential
encoding / decoding removes this uncertainty.
It can perform Manchester encoding. Manchester
encoding ensures that the modulation has no DC
content and enough transitions (changes from 0 to 1 and
from 1 to 0) for the demodulator bit timing recovery to
function correctly, but does so at a doubling of the data
rate.
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It can perform Spectral Shaping. Spectral shaping
removes DC content of the bit stream, ensures
transitions for the demodulator bit timing recovery, and
makes sure that the transmitted spectrum does not have
discrete lines even if the transmitted data is cyclic. It
does so without adding additional bits, i.e. without
changing the data rate. Spectral Shaping uses a self
synchronizing feedback shift register.
The encoder is programmed using the register
AX5051_ENCODING, details and recommendations on
usage are given in the AX5051 Programming Manual.
Framing and FIFO
Most radio systems today group data into packets. The
framing unit is responsible for converting these packets into
a bitstream suitable for the modulator, and to extract
packets from the continuous bitstream arriving from the
demodulator.
The Framing unit supports four different modes:
HDLC
Raw
Raw with Preamble Match
802.15.4 Compliant
The microcontroller communicates with the framing unit
through a 4 level × 10 bit FIFO. The FIFO decouples
microcontroller timing from the radio (modulator and
demodulator) timing. The bottom 8 bits of the FIFO contain
transmit or receive data. The top 2 bit are used to convey
meta information in HDLC and 802.15.4 modes. They are
unused in Raw and Raw with Preamble Match modes. The
meta information consists of packet begin / end information
and the result of CRC checks.
The framing unit contains one FIFO. Its direction is
switched depending on whether transmit or receive mode is
selected.
The FIFO can be operated in polled or interrupt driven
modes. In polled mode, the microcontroller must
periodically read the FIFO status register or the FIFO count
register to determine whether the FIFO needs servicing.
In interrupt mode EMPTY, NOT EMPTY, FULL, NOT
FULL and programmable level interrupts are provided.
Interrupts are acknowledged by removing the cause for the
interrupt, i.e. by emptying or filling the FIFO.
To lower the interrupt load on the microcontroller, one of
the DMA channels may be instructed to transfer data
between the transceiver FIFO and the XRAM memory. This
way, much larger buffers can be realized in XRAM, and
interrupts need only be serviced if the larger XRAM buffers
fill or empty.
HDLC Mode
NOTE: HDLC mode follows HighLevel Data Link
Control (HDLC, ISO 13239) protocol.
HDLC Mode is the main framing mode of the
AX8052F151. In this mode, the AX8052F151 performs
automatic packet delimiting, and optional packet
correctness check by inserting and checking a cyclic
redundancy check (CRC) field.
The packet structure is given in the following table.
Table 20.
Flag Address Control Information FCS Flag
8 bit 8 bit 8 or 16 bit Variable length, 0 or more bits in multiples of 8 16 / 32 bit 8 bit
HDLC packets are delimited with flag sequences of
content 0x7E.
In AX8052F151 the meaning of address and control is
user defined. The Frame Check Sequence (FCS) can be
programmed to be CRCCCITT, CRC16 or CRC32.
The receiver checks the CRC, the result can be retrieved
from the FIFO, the CRC is appended to the received data.
For details on implementing a HDLC communication see
the AX5051 Programming Manual.
Raw Mode
In Raw mode, the AX8052F151 does not perform any
packet delimiting or byte synchronization. It simply
serializes transmit bytes and deserializes the received
bitstream and groups it into bytes.
This mode is ideal for implementing legacy protocols in
software.
Raw Mode with Preamble Match
Raw mode with preamble match is similar to raw mode.
In this mode, however, the receiver does not receive
anything until it detects a user programmable bit pattern
(called the preamble) in the receive bitstream. When it
detects the preamble, it aligns the deserialization to it.
The preamble can be between 4 and 32 bits long.
802.15.4 (ZigBee) DSSS
802.15.4 uses binary phase shift keying (PSK) with
300 kbit/s (868 MHz band) or 600 kbit/s (915 MHz band) on
the radio. The usable bit rate is only a 15
th
of the radio bit
rate, however. A spreading function in the transmitter
expands the user bit rate by a factor of 15, to make the
transmission more robust. The despreader function of the
receiver undoes that.
In 802.15.4 mode, the AX8052F151 framing unit
performs the spreading and despreading function according
to the 802.15.4 specification. In receive mode, the framing
unit will also automatically search for the 802.15.4
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preamble, meaning that no interrupts will have to be
serviced by the microcontroller until a packet start is
detected.
The 802.15.4 is a universal DSSS mode, which can be
used with any modulation or data rate as long as it does not
violate the maximum data rate of the modulation being used.
Therefore the maximum DSSS data rate is 16 kbps for FSK
and 40 kbps for ASK and PSK.
RX AGC and RSSI
AX8052F151 features two receiver signal strength
indicators (RSSI):
1. RSSI before the digital IF channel filter.
The gain of the receiver is adjusted in order to
keep the analog IF filter output level inside the
working range of the ADC and demodulator. The
register AX5051_AGCCOUNTER contains the
current value of the AGC and can be used as an
RSSI. The step size of this RSSI is 0.625 dB. The
value can be used as soon as the RF frequency
generation subsystem has been programmed.
2. RSSI behind the digital IF channel filter.
The demodulator also provides amplitude
information in the AX5051_TRK_AMPLITUDE
register. By combining both the
AX5051_AGCCOUNTER and the
AX5051_TRK_AMPLITUDE registers, a high
resolution (better than 0.1 dB) RSSI value can be
computed at the expense of a few arithmetic
operations on the microcontroller. Formulas for
this computation can be found in the AX5051
Programming Manual.
Modulator
Depending on the transmitter settings the modulator
generates various inputs for the PA:
Table 21.
Modulation Bit = 0 Bit = 1 Main Lobe Bandwidth Max. Bitrate
ASK PA off PA on BW = BITRATE 600 kBit/s
FSK/MSK
Df = f
deviation
Df = +f
deviation
BW = (1 + h) BITRATE 350 kBit/s
PSK
DF = 0° DF = 180°
BW = BITRATE 600 kBit/s
h = modulation index. It is the ratio of the
deviation compared to the bitrate;
f
deviation
= 0.5hBITRATE, AX8052F151 can
demodulate signals with h < 32.
ASK = amplitude shift keying
FSK = frequency shift keying
MSK = minimum shift keying; MSK is a special case
of FSK, where h = 0.5, and therefore
f
deviation
= 0.25BITRATE; the advantage of
MSK over FSK is that it can be demodulated
more robustly.
PSK = phase shift keying
OQPSK = offset quadrature shift keying. The
AX8052F151 supports OQPSK. However,
unless compatibility to an existing system is
required, MSK should be preferred.
All modulation schemes are binary.
Automatic Frequency Control (AFC)
The AX8052F151 has a frequency tracking register
AX5051_TRKFREQ to synchronize the receiver frequency
to a carrier signal. For AFC adjustment, the frequency offset
can be computed with the following formula:
Df +
TRKFREQ
2
16
BITRATE FSKMUL
FSKMUL is the FSK oversampling factor, it depends on
the FSK bit rate and deviation used. To determine it for a
specific case, see the AX5051 Programming Manual. For
modulations other than FSK, FSKMUL = 1.
PWRMODE Register
The AX8052F151 transceiver features its own
independent power management, independent from the
microcontroller. While the microcontroller power mode is
controlled through the PCON register, the
AX5051_PWRMODE register controls which parts of the
transceiver are operating.
Table 22. PWRMODE REGISTER
AX5051_PWRMODE
Register
Name Description
0000 POWERDOWN All digital and analog transceiver functions, except the register file, are disabled. VREG is
reduced to conserve leakage power. The registers are still accessible.
0100 VREGON All digital and analog transceiver functions, except the register file, are disabled. VREG,
however is at its nominal value for operation, and all registers are accessible.
0101 STANDBY The crystal oscillator is powered on; receiver and transmitter are off.

AX8052F151-2-TB05

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ON Semiconductor
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RF System on a Chip - SoC RF-MICROCONTROLLER
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