AX8052F151
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4
Table 1. PIN FUNCTION DESCRIPTIONS
Symbol Pin(s) Type Description
GND 1 P Ground
GND 2 P Ground
VDDA 3 P Power supply, must be supplied with regulated voltage VREG
GND 4 P Ground
ANTP 5 A Antenna input/output
ANTN 6 A Antenna input/output
GND 7 P Ground
VDDA 8 P Power supply, must be supplied with regulated voltage VREG
TST1 9 I Connected to GND
TST 10 I Connected to GND
VDD_IO 11 P Unregulated power supply (battery input)
SYSCLK 12 I/O/PU System Clock Output
PC4 13 I/O/PU General Purpose IO
PC3 14 I/O/PU General Purpose IO
PC2 15 I/O/PU General Purpose IO
PC1 16 I/O/PU General Purpose IO
PC0 17 I/O/PU General Purpose IO
PB0 18 I/O/PU General Purpose IO
PB1 19 I/O/PU General Purpose IO
PB2 20 I/O/PU General Purpose IO
PB3 21 I/O/PU General Purpose IO
PB4 22 I/O/PU General Purpose IO
PB5 23 I/O/PU General Purpose IO
PB6 24 I/O/PU General Purpose IO, DBG_DATA
PB7 25 I/O/PU General Purpose IO, DBG_CLK
DBG_EN 26 I/PD In−Circuit Debugger Enable
RESET_N 27 I/PU Optional reset pin
If this pin is not used it must be connected to VDD_IO
GND 28 P Ground
VDD_IO 29 P Unregulated power supply (battery input)
PA0 30 I/O/A/PU General Purpose IO
PA1 31 I/O/A/PU General Purpose IO
PA2 32 I/O/A/PU General Purpose IO
PA3 33 I/O/A/PU General Purpose IO
PA4 34 I/O/A/PU General Purpose IO
PA5 35 I/O/A/PU General Purpose IO
PA6 36 I/O/A/PU General Purpose IO
PA7 37 I/O/A/PU General Purpose IO
VREG 38 P Regulated output voltage
VDDA pins must be connected to this supply voltage
A 1 mF low ESR capacitor to GND must be connected to this pin
CLK16P 39 A Crystal oscillator input/output (RF reference)
