AX8052F151
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Table 22. PWRMODE REGISTER
AX5051_PWRMODE
Register
DescriptionName
1000 SYNTHRX The synthesizer is running on the receive frequency. Transmitter and receiver are still off.
This mode is used to let the synthesizer settle on the correct frequency for receive.
1001 FULLRX Synthesizer and receiver are running.
1100 SYNTHTX The synthesizer is running on the transmit frequency. Transmitter and receiver are still off.
This mode is used to let the synthesizer settle on the correct frequency for transmit.
1101 FULLTX Synthesizer and transmitter are running. Do not switch into this mode before the
synthesizer has completely settled on the transmit frequency (in SYNTHTX mode),
otherwise spurious spectral transmissions will occur.
Table 23. A TYPICAL AX5051_PWRMODE SEQUENCE FOR A TRANSMIT SESSION
Step PWRMODE Remarks
1 POWERDOWN
2 STANDBY The settling time is dominated by the crystal used, typical value 3 ms.
3 SYNTHTX
The synthesizer settling time is 5 – 50 ms depending on settings, see section AC Characteristics
4 FULLTX Data transmission
5 SYNTHTX This step must be programmed after FULLTX mode, or the device will not enter
POWERDOWN or STANDBY mode.
6 POWERDOWN
Table 24. A TYPICAL AX5051_PWRMODE SEQUENCE FOR A RECEIVE SESSION
Step PWRMODE [3:0] Remarks
1 POWERDOWN
2 STANDBY The settling time is dominated by the crystal used, typical value 3 ms.
3 SYNTHRX
The synthesizer settling time is 5 – 50 ms depending on settings, see section AC Characteristics
4 FULLRX Data reception
5 POWERDOWN
Voltage Regulator
The AX8052F151 transceiver uses its own dedicated
on−chip voltage regulator to create a stable supply voltage
for the transceiver circuitry at pin VREG from the primary
supply VDD_IO. All VDDA pins of the device must be
connected to VREG. The antenna pins ANTP and ANTN
must be DC biased to VREG. The I/O level of the digital pins
is VDD_IO.
The voltage regulator requires a 1 mF low ESR capacitor
at pin VREG.
In power−down mode the voltage regulator typically
outputs 1.7 V at VREG, if it is powered−up its output rises
to typically 2.5 V. At device power−up the regulator is in
power−down mode.
The voltage regulator must be powered−up before receive
or transmit operations can be initiated. This is handled
automatically when programming the device modes via the
AX5051_PWRMODE register.
Register VREG contains status bits that can be read to
check if the regulated voltage is above 1.3 V or 2.3 V, sticky
versions of the bits are provided that can be used to detect
low power events (brown−out detection).
