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SAM9N12/SAM9CN11/SAM9CN12 [SUMMARY DATASHEET]
11063HS–ATARM–27-Sep-13
1. Features
Core
ARM926EJ-S
™
ARM
®
Thumb
®
Processor running up to 400 MHz
16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
Memories
One 128-Kbyte internal ROM embedding standard or secure bootstrap routine.
One 32-Kbyte internal SRAM, single-cycle access at system speed
32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories
MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error Correcting Code (PMECC)
System running up to 133 MHz
Power-on Reset, Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real
Time Clock
Boot Mode Select Option, Remap Command
Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
Selectable 32768 Hz Low-power Oscillator, 16 MHz Oscillator, one PLL for the system and one PLL
optimized for USB
Six 32-bit-layer AHB Bus Matrix
Dual Peripheral Bridge with dedicated programmable clock
One dual port 8-channel DMA Controller
Advanced Interrupt Controller and Debug Unit
Two Programmable External Clock Signals
Low-power Mode
Shut Down Controller with four 32-bit battery backup registers
Clock Generator and Power Management Controller
Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
Peripherals
LCD Controller
USB Device Full Speed with dedicated On-Chip Transceiver
USB Host Full Speed with dedicated On-Chip Transceiver
One High speed SD card and SDIO Host Controller
Two Master/Slave Serial Peripheral Interfaces
Two Three-channel 32-bit Timer/Counters
One Synchronous Serial Controller
One Four-channel 16-bit PWM Controller
Two Two-wire Interfaces
Four USARTs, two UARTs, one DBGU
One 12-channel 10-bit Analog-to-Digital Converter with up to 5-wire resistive Touch screen support
Safety
Crystal Failure Detection
Independent Watchdog
Power-on Reset Cells
Write Protection Registers
SHA (SHA1 and SHA256) Compliant with FIPS Publication 180-2, see the device configuration table in
“Description”
