2
MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Common Features
• Full-duplex differential data links.
• Selectable speed range: 1.25 Gbaud or 0.625 Gbaud.
• Low power, approximately less than 1W under typical conditions, while operating in backplane
mode with all transceivers at full speed.
• Internal 8B/10B encoder/decoder that may be bypassed.
• Source synchronous parallel data input interfaces.
• Selectable: Source aligned or source centered timing on the receiver output interfaces.
• DDR (RGMII/RTBI), source synchronous, 4-/5-bit optional interfaces.
• Parallel interfaces may be either LVTTL or SSTL_2.
• Transmit data clock is selectable between per-channel transmit clock or channel ‘A’ transmit clock.
• Received data may be clocked to the recovered clock or to the reference clock frequencies.
• Unused transceiver channels may be individually disabled.
• Drives 50-
Ω
or 75-
Ω
media (100-
Ω
or 150-
Ω
differential) for lengths of up to 1.5 meters
board/backplane, or 10 meters of coax.
• Tolerates a frequency offset between the transmitter and receiver of +
250ppm.
• Link inputs have on-chip receiver termination and are “hot swap” compatible.
• Differential LVPECL reference clock input with single-ended LVCMOS input option.
• Two single-ended buffered reference clock outputs to be used as clock source for associated MAC
interface logic.
• Built-in, at speed, self test for production testing and on-board diagnostics.
•
IEEE
Std 1149.1
JTAG boundary scan test support.
Backplane Application Features
• Link-to-link synchronization supports aligned, multi-channel, word transfers. Synchronization
mechanism tolerates up to 40 bit-times of link-to-link media delay skew.
• Supports three options for word synchronization including disparity based word sync events for
compatibility with legacy transceivers.
• Selectable COMMA code group alignment mode enables aligned or unaligned transfers.
Ethernet Friendly Features
• Provides the PCS and PMA layers for Ethernet PHYs as specified in
IEEE Std 802.3-2000
.
• MDIO slave interface and registers as defined in
IEEE Std 802.3-2000
is fully supported.
• Supports rate adaption within IPG for Jumbo frames up to 16K bytes.
General Parameters
The MC92603 and MC92604 are designed in a 0.25
µ
lithography, HiP4 CMOS, 5 layer metal process.
The core logic and high speed serial link I/O require a 1.8 Volt power source while the parallel data
interfaces may be 3.3 V LVTTL or 2.5 V SSTL.
The MC92603 is packaged in a 256 pin MAP Ball Grid Array which has a body size of 17 mm square. The
package for the MC92604 is TBD.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
