MC92603VF Datasheet MC92603VF, MC92604VM, MC92604ZT | P13-P15

MOTOROLA MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers 13

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

GMII Interface

GMII Mode is enabled by setting the TBIE input low and COMPAT input high. When in this mode the

receiver should be connected to a standard Gigabit Ethernet MAC as shown in Table 9.

Initially the receiver must attain byte alignment through the detection of 4 COMMA code groups with the

same alignment as explained previously. Next the receiver must attain stream alignment per Figure 36-9 of

‘IEEE Std 802.3-2002.’

The RECV_x_ERR output remains high until both alignments are attained.

The receiver will now search for a Start_of_Packet code group (/S/). Upon the detection of a Start_of_Packet

the receiver will replace that code group with a preamble code group (55 hex) and present this data on the

receiver data output RECV_x_7 through RECV_x_0 as the RECV_x_DV output is raised. This is per

Figures 36-7a and 36-7b of ‘IEEE Std 802.3-2002.’

Data will continue to be presented on the data outputs and the RECV_x_DV output will remain high until

an End_of_Packet code group (/T/) is received. At this point the RECV_x_DV output will lowered and

remain low until the next Start_of_Packet is received. When the End_of_Packet code group (/T/) is received

the RECV_x_DV output will lowered after the previous data code group is presented on the receiver data

interface (RECV_x_7 through RECV_x_0).

TBI Interface

TBI Mode is enabled by setting the TBIE and COMPAT inputs high. When in this mode, the MC92603 will

conform to the IEEE Std 802.3-2002 TBI interface signals and protocol. The complete TBI connection to

a standard Ethernet MAC is show in

Table 10.

Table 9. GMII Connection to Standard Ethernet MAC

IEEE 802.3_2002 Signal

Name

Function

Direction

(relative to GEt)

GEt Port Name

GTX_CLK Transmit Clock Input XMIT_x_CLK

TX_EN Transmit Enable Input XMIT_x_ENABLE

TX_ER Force Error on Transmitted Byte Input XMIT_x_ERR

TXD<7:0> Transmit Data Input XMIT_x_[7:0]

RX_CLK Receive Clock Output RECV_x_CLK

RXD<7:0> Receive Data Output RECV_x_[7:0]

RX_ER Receiver has detected an error Output RECV_x_ERR

RX_DV Receiver has detected data Output RECV_x_DV

MDC Management Data Clock Input MD_CLK

MDIO Management Data Input/Output Bidirectional MD_DATA

The following inputs must be externally pulled up/down as indicated

Pull Up Management Interface Enable Input MD_ENABLE

Variable (PUP/PUD) MDIO PHY Address Input MD_ADR[4:2]

Pull Down Disable unused Transmitter Input Input XMIT_x_K

Pull Down Conﬁguration Input - put in 8 bit mode Input TBIE

Pull Up Conﬁguration Input - put in

synchronized mode

Input BSYNC

Pull Down Conﬁguration Input - disable word

alignment

Input WSYNC1 & WSYNC0

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14 MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

The receiver interface works similar to the backplane 10-bit mode except that word synchronization is not

supported and non-aligned operation is not allowed. Also in this mode the XMIT_x_K input is not required

for the transmitter so it is used to “enable COMMA detect”. The MC92603/4 will always initially perform

even/odd alignment to the ﬁrst IDLE (K28.5) code-group encountered. If XMIT_x_K is low it will NOT

realign to any future IDLEs that may appear in the data stream. Data out of the receiver is even/odd aligned

with the two output clocks. IDLEs (K28.5 code groups) are initially aligned with the rising edge of

RECV_x_CLK_B. If “enable COMMA detect” is enabled (XMIT_x_K is high) then a data code group may

be repeated to force this alignment if an IDLE is encountered in an ODD code group.

MDIO

The MDIO (Management Data Input/Output) interface as deﬁned in Clause 22 of IEEE Std 802.3-2002 is

supported by the MC92603and MC92604 Gigabit Ethernet transceivers. Details for protocol and electrical

characteristics are available in the standard.

The MC92603/4 chip MDIO interface consists of 1 enable input, 3 or 4 address inputs, one clock input, and

one bidirectional data signal.

Some users may desire to use the MDIO interface, others may not. If the MDIO interface is to be used then

the MD_ENABLE input must be tied high. The MDIO interface is available whether COMPAT is enabled

or not. On power-up the MC92603/4 will always assume the default conﬁguration deﬁned by the pins of the

device. The conﬁguration can then be changed via the MDIO interface regardless of the application

operating mode. If MDIO is not used (MD_ENABLE is low) The MC92603/4 will operate in the default

conﬁguration.

The MDIO interface is a multidrop serial interface and each part must have a unique PHY Address. In the

MC92603 each channel is addressed separately. The base address to each transceiver must be mod 4. This

address is read from three input ports that must be externally pulled up or pulled down to furnish a unique

address for each part connected to a MDIO bus. The two least signiﬁcant bits of the 5 bit address, are used

Table 10. TBI Connection to Standard Ethernet MAC

802.3-2002 Signal Function

Direction

(relative to

GEt )

GEt Port Name

PMA_TX_CLK Transmit Clock Input XMIT_x_CLK

tx_code_group<9:0> Transmit Data Input XMIT_x_ERR,XMIT_x_ENABLE,XMIT_x_[7:0]

EWRAP Enable Data Wraparound Input XMIT_x_LBE

EN_CDET Enable COMMA detect Input XMIT_x_K

COM_DET Receiver Detected a COMMA Output RECV_x_COMMA

rx_code_group<9:0> Receive Data Output RECV_x_ERR, RECV_x_DV, RECV_x_[7:0]

-LCK_REF Enable Lock to Reference Input RCCE (normally low, affects all 4 channels)

PMA_RX_CLK<0:1> Receive Clocks (both phases) Output RECV_x_CLK, RECV_x_CLK

The following output is available but is not a standard TBI signal

N/A Receiver Detected an error Output RECV_x_K

The following inputs must be externally pulled up/down as indicated

Pull Down Management Interface Enable Input MD_ENABLE

Variable (PUP/PUD) MDIO PHY Address Input MD_ADR[4:2]

Pull Up Conﬁguration Input TBIE

Pull Up Conﬁguration Input BSYNC

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MOTOROLA MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers 15

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

to uniquely identify each MC92603 channel (00 indicates Channel A, 01 = B, 10 = C, and 11 indicates

Channel D (The least signiﬁcant bit for the MC92604 determines channel A or B).

The 2.5 Mhz clock (MD_CLK) is sourced at the MDIO Master (MAC) and is used by each slave MDIO

device. The MC92603/4 are designed as MDIO slave devices.

The MDIO data signal (MD_DATA) is a bidirectional serial signal used to read and write management data

from/to the MDIO Registers.

The speciﬁcation calls for up to 64 registers to be supported by MDIO. Some registers MUST be included

as a minimum to meet the MDIO speciﬁcation. These are identiﬁed as the “basic” register set. Other

registers are optional and are considered part of the “extended” register set. The MC92603 and MC92604

have four sets of MDIO registers (1 per transceiver). Resisters for address 0 through 6 and 15 through 17,

as deﬁned in the speciﬁcation, are fully supported. the registers 7 through 14 and 18 through 31 are NOT

supported in the MC92603/4.

Test Features

TheMC92603 and MC92604 supports test modes for in-system BIST testing. They also has a ﬁve terminal

JTAG interface as described in IEEE Std 1149.1.

Each channel of the transceiver may be individually conﬁgured for digital loop back where the transmitted

data is looped back to its receiver independent of the receiver’s link inputs. The code groups transmitted are

controlled by the normal transmitter controls. If the transceiver is working properly, the data/control code

groups transmitted are received by the receiver. This allows system logic to use various data sequences to

test the operation of the transceiver.

The loop-back signals are electrically isolated from the output signal pads. Therefore, if the outputs are

shorted, or otherwise restricted, the loop-back signals still operate normally.

The receiver’s link input signals are also electrically isolated during loop back mode, such that their state

does not affect the loop back path.

LBOE controls the state of the link output signals during Loop Back testing. If LBOE is low then

XLINK_x_P/XLINK_x_N are held to low/high respectively. If LBOE is high then data will be present on

the outputs.

The MC92603/4 has an integrated, 23rd order, Pseudo-Noise (PN) pattern generator. Stimulus from this

generator may be used for system testing. The receiver, has a 23rd order signature analyzer that is

synchronized to the incoming PN stream and may be used to count code group mismatch errors relative to

the internal PN reference pattern. This implementation of the 23-bit PN generator and analyzer uses the

polynomial: f = 1 + x

+ x

The total mismatch error count is presented on the receiver interface signals and is reset to zero when BIST

mode is entered. The count is updated continuously while in BIST mode. The value of this eight-bit error

count is sticky in that the count will not wrap to zero upon overﬂow, but rather, stays at the maximum count

value (11111111). In ALL BERT test modes an error counter is maintained in a MDIO Register for each

speciﬁc channel.

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