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TSE2002GB2A1NCG

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No Acknowledge Bit (NACK)
The no-acknowledge bit is used to indicate the completion of a block read operation, or an attempt to modify a write-protected register. The bus
master releases Serial Data (SDA) after sending eight bits of data, and during the 9th clock pulse period, and does not pull Serial Data (SDA) Low.
Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven
Low.
Memory Addressing
To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master
sends the Device Select Code, shown in the next table (on Serial Data (SDA), most significant bit first).
Device Select Code
Notes:
1. The most significant bit, b7, is sent first.
2. SA0, SA1, and SA2 are compared against the respective external pins on the TSE2002GB2A1.
The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Select Address (SA2, SA1, SA0). To address the memory array, the
4-bit Device Type Identifier is 1010b; to access the write-protection settings, it is 0110b; and to access the Temperature Sensor settings is 0011b.
Up to eight memory devices can be connected on a single I
2
C bus. Each one is given a unique 3-bit code on the Chip Enable (SA0, SA1, SA2)
inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable
(SA0, SA1, SA2) inputs.
The 8th bit is the Read/Write bit (R/W#). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If
the device does not match the SPD Device Select code, the SPD section deselects itself from the bus, and goes into Standby mode. The I
2
C oper-
ating modes are shown in the following table.
Memory Area
Function
Device Type Identifier Select Address Signals R/W#
b7
1
b6 b5 b4 b3 b2 b1 b0
Read/Write SPD Memory 1 0 1 0 SA2 SA1 SA0 R/W#
Set Write Protection (SWP)
0110
V
SSSPD
V
SSSPD
V
HV
0
Clear Write Protection (CWP) V
SSSPD
V
DDSPD
V
HV
0
Permanently Set Write Protection (PSWP)
2
SA2 SA1 SA0 0
Read SWP V
SSSPD
V
SSSPD
V
HV
1
Read PSWP
2
SA2 SA1 SA0 1
Read/Write Temperature Registers 0 0 1 1 SA2 SA1 SA0 R/W#
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I
2
C Operating Modes
Device Reset and Initialization
In order to prevent inadvertent Write operations during Power-up, a Power-On Reset (POR) circuit is included.
At Power-up (phase during which V
DDSPD
is lower than V
DDSPDmin
but increases continuously), the device will not respond to any instruction until
V
DDSPD
has reached the Power On Reset threshold voltage (this threshold is lower than the minimum V
DDSPD
operating voltage defined in the DC
AND AC PARAMETERS tables). Once V
DDSPD
has passed the POR threshold, the device is reset. The actual POR threshold voltage will be imple-
mentation dependent and is not defined in this document.
The device is delivered with all bits in the EEPROM memory array set to ' 1' (each byte contains 0xFF).
Prior to selecting the memory and issuing instructions, a valid and stable V
DDSPD
voltage must be applied. This voltage must remain stable and
valid until the end of the transmission of the instruction and for a Write instruction, until the completion of the internal write cycle (t
W
).
At Power-down (phase during which V
DDSPD
decreases continuously), as soon as V
DDSPD
drops below the minimum operating voltage, the device
stops responding to commands, and remains in reset until the POR threshold voltage is reached.
Mode R/W# Bit Bytes Initial Sequence
SPD Current Address Read 1 1 START, Device Select, R/W# = 1
SPD Random Address Read
0
1
START, Device Select, R/W# = 0, Address
1 reSTART, Device Select, R/W# = 1
SPD Sequential Read 1 >
1 Similar to Current or Random Address Read
SPD Byte Write 0 1 START, Device Select, R/W# = 0, data, STOP
SPD Page Write 0 <
16 START, Device Select, R/W# = 0, data, STOP
TS Write 0 2 START, Device Select, R/W#=0, pointer, data, STOP
TS Read 1 2 START, Device Select, R/W#=1, pointer, data, STOP
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Software Write Protect
The TSE2002GB2A1 has three software write-protection features, allowing the bottom half of the memory area (addresses 0x00 to 0x7F) to be
temporarily or permanently write protected.
Software write-protection is handled by three instructions:
SWP: Set Write Protection
CWP: Clear Write Protection
PSWP: Permanently Set Write Protection
The level of write-protection (set or cleared) that has been defined using these instructions, remains defined even after a power cycle.
Result of Setting the Write Protection
SWP and CWP
If the software write-protection has been set with the SWP instruction, it can be cleared again with a CWP instruction.
The two instructions (SWP and CWP) have the same format as a Byte Write instruction, but with a different Device Type Identifier (refer to the I
2
C
Operating Modes table). Like the Byte Write instruction, it is followed by an address byte and a data byte, but in this case the contents are all “Don't
Care” (refer to the Setting the Write Protection figure). Another difference is that the voltage, V
HV
, must be applied on the SA0 pin, and specific logical
levels must be applied on the other two (SA1 and SA2, as shown in the I
2
C Operating Mode table).
PSWP
If the software write-protection has been set with the PSWP instruction, the first 128 bytes of the memory are permanently write-protected. This
write-protection cannot be cleared by any instruction, or by power-cycling the device. Also, once the PSWP instruction has been successfully
executed, the TSE2002GB2A1 no longer acknowledges any instruction (with a Device Type Identifier of 0110) to access the write-protection settings.
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TSE2002GB2A1NCG

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Buy TSE2002GB2A1NCG
Manufacturer:
IDT
Description:
Board Mount Temperature Sensors Temp Sensor with Integrated EEPROM for Memory
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