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TSE2002GB2A1NCG

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Read Mode Sequences
Random Address Read
A dummy Write is first performed to load the address into this address counter (refer to the Read Mode Sequence figure) but without sending a
Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the R/W# bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with
a Stop condition.
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the R/W# bit set to 1.
The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master
terminates the transfer with a Stop condition, as shown in the Read Mode Sequence figure, without acknowledging the byte.
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Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output,
and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must generate a Stop condition (refer to the Read Mode Sequence figure). The output data comes from
consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the
address counter 'rolls-over', and the device continues to output data from memory address 0x00.
Acknowledge in Read Mode
For all Read commands to the SPD, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does
not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and returns to an idle state to await the next valid START
condition. This has no effect on the TS operational status.
Acknowledge When Writing Data or Defining Write Protection (Instructions with R/W# Bit=0)
Note 1: Software must accept either return code.
Acknowledge When Reading the Write Protection (Instructions with R/W# Bit=1)
Note: X = Set or Not Set.
Temperature Sensor (TS) Device Operation
The TSE2002GB2A1 Temperature Register Set is accessed though the I
2
C address 0011_bbb_R/W#. The “bbb” denotes the current state of SA2,
SA1, and SA0. In the event SA0 is in the high voltage state, the device interprets the voltage as a logic '1' at the pin. The Temperature Register Set
stores the temperature data, limits, and configuration values. All registers in the address space from 0x00 through 0x08 are 16-bit registers accessed
through block read and write commands as detailed in the TS Write Operation section.
Status Instruction ACK Address ACK Data Byte ACK Write Cycle
(t
W
)
Permanently
Protected
PSWP, SWP, or CWP NoACK Not Significant NoACK Not Significant NoACK No
Page or byte write in
lower 128 bytes
ACK Address ACK Data ACK or
NoACK
1
Yes
Protected with
SWP
SWP NoACK Not Significant NoACK Not Significant NoACK No
CWP ACK Not Significant ACK Not Significant ACK Yes
PSWP ACK Not Significant ACK Not Significant ACK Yes
Page or byte write in
lower 128 bytes
ACK Address ACK Data ACK or
NoACK
1
Yes
Not Protected PSWP, SWP, or CWP ACK Not Significant ACK Not Significant ACK Yes
Page or byte write ACK Address ACK Data ACK Yes
PSWP
Status
SWP Status Instruction ACK Address ACK Data Byte ACK
Set X Read PSWP NoACK Not Significant NoACK Not Significant NoACK
Not Set X Read PSWP ACK Not Significant NoACK Not Significant NoACK
Set X Read SWP NoACK Not Significant NoACK Not Significant NoACK
X Set Read SWP NoACK Not Significant NoACK Not Significant NoACK
Not Set Not Set Read SWP ACK Not Significant NoACK Not Significant NoACK
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TS Write Operations
Writing to the TSE2002GB2A1 Temperature Register Set is accomplished through a modified block write operation for two (2) data bytes. To main-
tain I
2
C compatibility, the 16 bit register is accessed through a pointer register, requiring the write sequence to include an address pointer in addition to
the Slave address. This indicates the storage location for the next two bytes received. The next figure shows an entire write transaction on the bus.
TS Register Write Operation
TS Read Operations
Reading data from the TS may be accomplished in one of two ways:
1. If the location latched in the Pointer Register is correct (for normal operation it is expected the same address will be read repeatedly for temper-
ature), the read sequence may consist of a Slave Address from the bus master followed by two bytes of data from the device; or
2. The pointer register is loaded with the correct register address, and the data is read. The sequence to preset the pointer register is shown in the
I
2
C Write to Pointer Register figure, and the preset pointer read is shown in the I
2
C Preset Pointer Register Word Read figure. If it is desired to read
random address each cycle, the complete Pointer Write, Word Read sequence is shown in the I
2
C Pointer Write Register Word Read figure.
The data byte has the most significant bit first. At the end of a read, this device can accept either Acknowledge (Ack) or No Acknowledge (No Ack)
from the Master (No Acknowledge is typically used as a signal for the slave that the Master has read its last byte).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

TSE2002GB2A1NCG

Mfr. #:
Buy TSE2002GB2A1NCG
Manufacturer:
IDT
Description:
Board Mount Temperature Sensors Temp Sensor with Integrated EEPROM for Memory
Lifecycle:
New from this manufacturer.
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