6 of 30 July 17, 2012
AC Characteristics
1. For a RESTART condition, or following a write cycle.
2. Guaranteed by design and characterization, not necessarily tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between falling edge of SCL and the falling or
rising edge of SDA.
4. The TSE2002GB2A1 does not initiate clock stretching which is an optional I
2
C bus feature
5. Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval
exceeds the value of t
TIMEOUT,MIN
. After the master in a transaction detects this condition, it must generate a stop condition
within or after the current data byte in the transfer process. Devices that have detected this condition must reset their
communication and be able to receive a new START condition no later than t
TIMEOUT,MAX
. Typical device examples include
the host controller and embedded controller and most devices that can master the SMBus. Some devices do not contain a clock
low drive circuit; this simple kind of device typically may reset its communications port after a start or stop condition. A
timeout condition can only be ensured if the device that is forcing the timeout holds SCL low for t
TIMEOUT,MAX
or longer.
6. The temperature sensor family of devices are not required to support the SMBus ALERT function.
Parameter Symbol
V
DDSPD
> 2.2 V
UnitsMin. Max.
Clock Frequency f
SCL
10 400 kHz
Clock Pulse Width High Time t
HIGH
600 ns
Clock Pulse Width Low Time t
LOW
5
1300 ns
Detect clock low timeout, Capabilities
Register bit 6 =1
t
TIMEOUT
6
25 35 ms
SDA Rise Time t
R
2
300 ns
SDA Fall Time t
F
2
20 300 ns
Data In Setup Time t
SU:DAT
100 ns
Data In Hold Time t
HD:DI
0ns
Data Out Hold Time t
HD:DAT
200 900 ns
Start Condition Setup Time t
SU:STA
1
600 ns
Start Condition Hold Time t
HD:STA
600 ns
Stop Condition Setup Time t
SU:STO
600 ns
Time Between Stop Condition and Next
Start Condition
t
BUF
1300 ns
Write Time t
W
4.5 ms
