Data Sheet E1831E30 (Ver. 3.0)
10
EDB4064B3PB
2. Electrical Specifications
2.1 DC Characteristics 1
(TC = -30°C to +85°C, VDD1 = 1.70V to 1.95V, VDD2, VDDQ = 1.14V to 1.30V)
Table 3 IDD Specification Parameters and Operating Conditions
Symbol Power
Supply
1066 800 Unit Parameter/Condition
max. max.
IDD0_1 VDD1 14 14 mA All devices in operating one bank active-precharge
tCK = tCK(avg)min; tRC = tRCmin; CKE is HIGH;
/CS is HIGH between valid commands;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD0_2 VDD2 80 76 mA
IDD0_IN VDDQ 2.0 2.0 mA
IDD2P_1 VDD1 0.6 0.6 mA All devices in idle power-down standby current
tCK = tCK(avg)min; CKE is LOW; /CS is HIGH; All banks idle;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD2P_2 VDD2 1.6 1.6 mA
IDD2P_IN VDDQ 0.2 0.2 mA
IDD2PS_1 VDD1 0.6 0.6 mA All devices in idle power-down standby current with clock stop
CK=LOW, /CK=HIGH; CKE is LOW; /CS is HIGH; All banks idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD2PS_2 VDD2 1.6 1.6 mA
IDD2PS_IN VDDQ 0.2 0.2 mA
IDD2N_1 VDD1 1.2 1.2 mA All devices in idle non power-down standby current
tCK = tCK(avg)min; CKE is HIGH; /CS is HIGH; All banks idle;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD2N_2 VDD2 28 24 mA
IDD2N_IN VDDQ 2.0 2.0 mA
IDD2NS_1 VDD1 1.2 1.2 mA All devices in idle non power-down standby current with clock stop
CK=LOW, /CK=HIGH; CKE is HIGH; /CS is HIGH; All banks idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD2NS_2 VDD2 14 14 mA
IDD2NS_IN VDDQ 2.0 2.0 mA
IDD3P_1 VDD1 1.4 1.4 mA All devices in active power-down standby current
tCK = tCK(avg)min; CKE is LOW; /CS is HIGH; One bank active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD3P_2 VDD2 8.0 8.0 mA
IDD3P_IN VDDQ 0.2 0.2 mA
IDD3PS_1 VDD1 1.4 1.4 mA All devices in active power-down standby current with clock stop
CK=LOW, /CK=HIGH; CKE is LOW; /CS is HIGH; One bank active;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD3PS_2 VDD2 8.0 8.0 mA
IDD3PS_IN VDDQ 0.2 0.2 mA
IDD3N_1 VDD1 3.0 3.0 mA All devices in active non power-down standby current
tCK = tCK(avg)min; CKE is HIGH; /CS is HIGH; One bank active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD3N_2 VDD2 34 30 mA
IDD3N_IN VDDQ 2.0 2.0 mA
IDD3NS_1 VDD1 3.0 3.0 mA All devices in active non power-down standby current with clock stop
CK=LOW, /CK=HIGH; CKE is HIGH; /CS is HIGH; One bank active;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD3NS_2 VDD2 20 20 mA
IDD3NS_IN VDDQ 2.0 2.0 mA
IDD4R_1 VDD1 4.0 4.0 mA All devices in operating burst read
tCK = tCK(avg)min; /CS is HIGH between valid commands;
One bank active; BL = 4; RL = RLmin;
CA bus inputs are SWITCHING;
50% data change each burst transfer;
IDD4R_2 VDD2 320 250 mA
Data Sheet E1831E30 (Ver. 3.0)
11
EDB4064B3PB
IDD4W_1 VDD1 4.0 4.0 mA All devices in operating burst write
tCK = tCK(avg)min; /CS is HIGH between valid commands;
One bank active; BL = 4; WL = WLmin;
CA bus inputs are SWITCHING;
50% data change each burst transfer;
IDD4W_2 VDD2 360 280 mA
IDD4W_IN VDDQ 2.0 2.0 mA
IDD5_1 VDD1 46 46 mA All devices in all bank auto-refresh
tCK = tCK(avg)min; CKE is HIGH between valid commands;
tRC = tRFCabmin; Burst refresh;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
IDD5_2 VDD2 164 160 mA
IDD5_IN VDDQ 2.0 2.0 mA
IDD5AB_1 VDD1 4.0 4.0 mA All devices in all bank auto-refresh
tCK = tCK(avg)min; CKE is HIGH between valid commands; tRC = tREFI;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
IDD5AB_2 VDD2 30 24 mA
IDD5AB_IN VDDQ 2.0 2.0 mA
IDD5PB_1 VDD1 4.0 4.0 mA All devices in per bank auto-refresh
tCK = tCK(avg)min; CKE is HIGH between valid commands;
tRC = tREFI/8;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
IDD5PB_2 VDD2 30 24 mA
IDD5PB_IN VDDQ 2.0 2.0 mA
IDD8_1 VDD1 20 20 µA All devices in deep power-down
CK = LOW, /CK = HIGH; CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
IDD8_2 VDD2 20 20 µA
IDD8_IN VDDQ 20 20 µA
Notes: 1. IDD values published are the maximum of the distribution of the arithmetic mean.
2. IDD current specifications are tested after the device is properly initialized.
Table 3 IDD Specification Parameters and Operating Conditions (cont’d)
Symbol Power
Supply
1066 800 Unit Parameter/Condition
max. max.
Data Sheet E1831E30 (Ver. 3.0)
12
EDB4064B3PB
2.2 DC Characteristics 2
(TC = -30°C to +85°C, VDD1 = 1.70V to 1.95V, VDD2, VDDQ = 1.14V to 1.30V)
Table 4 IDD6 Full and Partial Array Self-Refresh Current
Parameter Symbol Value Unit Condition
Self-Refresh Current
+45°C
Full Array
IDD6_1 420 µA All devices in self-refresh
CK = LOW, /CK = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
IDD6_2 1200 µA
IDD6_IN 20 µA
1/2 Array
IDD6_1 260 µA
IDD6_2 780 µA
IDD6_IN 20 µA
1/4 Array
IDD6_1 200 µA
IDD6_2 540 µA
IDD6_IN 20 µA
1/8 Array
IDD6_1 170 µA
IDD6_2 420 µA
IDD6_IN 20 µA
Self-Refresh Current
+85°C
Full Array
IDD6_1 1100 µA
IDD6_2 3400 µA
IDD6_IN 200 µA
1/2 Array
IDD6_1 800 µA
IDD6_2 2400 µA
IDD6_IN 200 µA
1/4 Array
IDD6_1 700 µA
IDD6_2 1800 µA
IDD6_IN 200 µA
1/8 Array
IDD6_1 640 µA
IDD6_2 1500 µA
IDD6_IN 200 µA
Note: 1. IDD6 85°C is the maximum and IDD6 45°C is typical of the distribution of the arithmetic mean.
Table 5 Electrical Characteristics and Operating Conditions
Symbol min. max. Unit Parameter/Condition Note
IL -2 +2 µA
Input leakage current:
For CA, CKE, /CS, CK, /CK
Any input 0V VIN VDD2
(All other pins not under test = 0V)
2
IVREF -1
+1 µA
VREF supply leakage current:
VREFDQ = VDDQ/2 or VREFCA = VDD2/2
(All other pins not under test = 0V)
1
Notes: 1. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be
minimal.
2. Although DM is for input only, the DM leakage shall match the DQ and DQS, /DQS output leakage specification.

EDB4064B3PB-8D-F-D

Mfr. #:
Manufacturer:
Micron
Description:
IC DRAM 4G PARALLEL 216FBGA
Lifecycle:
New from this manufacturer.
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