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ADC0801S040/DB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
ADC0801S040_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 18 August 2008 10 of 19
NXP Semiconductors
ADC0801S040
Single 8 bits ADC, up to 40 MHz
Fig 4. Timing diagram
sample N + 1sample N
CLK
014aaa508
sample N + 2
sample N + 1sample N sample N + 2
50 %
VI
DATA
D0 to D7
V
DDO
0 V
50 %
DATA
N + 1
DATA
N
DATA
N − 1
DATA
N − 2
t
d(o)
t
w(clk)H
t
w(clk)L
t
d(s)
t
h(o)
ADC0801S040_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 18 August 2008 11 of 19
NXP Semiconductors
ADC0801S040
Single 8 bits ADC, up to 40 MHz
frequency on pin SLEEP = 100 kHz.
Fig 5. Timing diagram and test conditions of 3-state output delay time
LOW
HIGH
HIGH
LOW
ADC0801S040
V
DDD
V
DDD
S1
SLEEP
SLEEP
output
data
output
data
10 %
50 %
50 %
90 %
50 %
t
dLZ
t
dZL
t
dHZ
t
dZH
20 pF
3.3 kΩ
S1
TEST
V
DDD
t
dLZ
V
DDD
t
dZL
GND
t
dZH
t
dHZ
GND
014aaa496
Fig 6. Typical Integral Non-Linearity (INL) performance
014aaa501
−0.047
0.065
−0.160
0.178
0.291
A
(LSB)
−0.272
codes
0 27220468 136
ADC0801S040_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 18 August 2008 12 of 19
NXP Semiconductors
ADC0801S040
Single 8 bits ADC, up to 40 MHz
Fig 7. Typical Differential Non-Linearity (DNL) performance
014aaa502
−0.025
0.032
−0.84
0.091
0.150
A
(LSB)
−0.143
codes
0 27220468 136
Fig 8. Analog input settling-time diagram
014aaa497
code 255
code 0
50 %
50 %
CLK
VI
t
s(LH)
t
s(HL)
50 % 50 %
5 ns 5 ns
2 ns 2 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

ADC0801S040/DB

Mfr. #:
Buy ADC0801S040/DB
Manufacturer:
NXP Semiconductors
Description:
BOARD EVALUATION FOR ADC0801S040
Lifecycle:
New from this manufacturer.
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