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ADC0801S040/DB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
ADC0801S040_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 18 August 2008 4 of 19
NXP Semiconductors
ADC0801S040
Single 8 bits ADC, up to 40 MHz
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 2. Pin configuration
ADC0801S
040TS
CLK V
DDO
SLEEP D7
V
DDD
D6
V
SSD
D5
V
DDA
D4
V
SSA
D3
RB D2
RM D1
VI D0
RT V
SSO
014aaa494
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Table 3. Pin description
Symbol Pin Description
CLK 1 clock input
SLEEP 2 sleep mode input
V
DDD
3 digital supply voltage (2.7 V to 5.5 V)
V
SSD
4 digital ground
V
DDA
5 analog supply voltage (2.7 V to 5.5 V)
V
SSA
6 analog ground
RB 7 reference voltage BOTTOM input
RM 8 reference voltage MIDDLE
VI 9 analog input voltage
RT 10 reference voltage TOP input
V
SSO
11 output stage ground
D0 12 data output; bit 0 (Least Significant Bit (LSB))
D1 13 data output; bit 1
D2 14 data output; bit 2
D3 15 data output; bit 3
D4 16 data output; bit 4
D5 17 data output; bit 5
ADC0801S040_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 18 August 2008 5 of 19
NXP Semiconductors
ADC0801S040
Single 8 bits ADC, up to 40 MHz
8. Limiting values
[1] The supply voltages V
DDA
, V
DDD
and V
DDO
may have any value between −0.3 V and +7.0 V provided that
the supply voltage ∆V
DD
remains as indicated.
9. Thermal characteristics
10. Characteristics
D6 18 data output; bit 6
D7 19 data output; bit 7 (Most Significant Bit (MSB))
V
DDO
20 positive supply voltage for output stage (2.7 V to 5.5 V)
Table 3. Pin description
…continued
Symbol Pin Description
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DDA
analog supply voltage
[1]
−0.3 +7.0 V
V
DDD
digital supply voltage
[1]
−0.3 +7.0 V
V
DDO
output supply voltage
[1]
−0.3 +7.0 V
∆V
DD
supply voltage difference V
DDA
− V
DDD
;
V
DDD
− V
DDO
;
V
DDA
− V
DDO
−0.1 +4.0 V
V
I
input voltage referenced to
V
SSA
−0.3 +7.0 V
V
i(clk)(p-p)
peak-to-peak clock input voltage referenced to
V
SSD
-V
DDD
V
I
O
output current - 10 mA
T
stg
storage temperature −55 +150 °C
T
amb
ambient temperature −20 +75 °C
T
j
junction temperature - 150 °C
Table 5. Thermal characteristics
Symbol Parameter Condition Value Unit
R
th(j-a)
thermal resistance from junction to
ambient
in free air 120 K/W
Table 6. Characteristics
V
DDA
=V5toV6=3.3V;V
DDD
=V3toV4=3.3V;V
DDO
= V20 to V11 = 3.3 V; V
SSA
,V
SSD
and V
SSO
shorted together; V
i(a)(p-p)
= 1.84 V; C
L
= 20 pF; T
amb
= 0
°
C to 70
°
C; typical values measured at T
amb
= 25
°
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
DDA
analog supply voltage 2.7 3.3 5.5 V
V
DDD
digital supply voltage 2.7 3.3 5.5 V
V
DDO
output supply voltage 2.5 3.3 5.5
ADC0801S040_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 18 August 2008 6 of 19
NXP Semiconductors
ADC0801S040
Single 8 bits ADC, up to 40 MHz
∆V
DD
supply voltagedifference V
DDA
− V
DDD
−0.2 - +0.2 V
V
DDD
− V
DDO
−0.2 - +2.25 V
I
DDA
analog supply current - 4 6 mA
I
DDD
digital supply current - 5 8 mA
I
DDO
output supply current f
clk
= 40 MHz; ramp input;
C
L
=20pF
-12mA
P
tot
total power dissipation V
DDA
=V
DDD
=V
DDO
= 3.3 V - 30 53 mW
Inputs
Clock input CLK (Referenced to V
SSD
)
[1]
V
IL
LOW-level input voltage 0 - 0.3 V
DDD
V
V
IH
HIGH-level input voltage V
DDD
≤ 3.6 V 0.6 V
DDD
-V
DDD
V
V
DDD
> 3.6 V 0.7 V
DDD
-V
DDD
V
I
IL
LOW-level input current V
clk
= 0.3 V
DDD
−10 +1µA
I
IH
HIGH-level input current V
clk
= 0.7 V
DDD
--5µA
Z
i
input impedance f
clk
= 40 MHz - 4 - kΩ
C
i
input capacitance f
clk
= 40 MHz - 3 - pF
Input SLEEP (Referenced to V
SSD
); see Table 8
V
IL
LOW-level input voltage 0 - 0.3 V
DDD
V
V
IH
HIGH-level input voltage V
DDD
≤ 3.6 V 0.6 V
DDD
-V
DDD
V
V
DDD
> 3.6 V 0.7 V
DDD
-V
DDD
V
I
IL
LOW-level input current V
IL
= 0.3 V
DDD
−1- - µA
I
IH
HIGH-level input current V
IH
= 0.7 V
DDD
--+1µA
Analog input VI (Referenced to V
SSA
)
I
IL
LOW-level input current V
I
= V
RB
-0-µA
I
IH
HIGH-level input current V
I
= V
RT
-9-µA
Z
i
input impedance f
i
= 1 MHz - 20 - kΩ
C
i
input capacitance f
i
= 1 MHz - 2 - pF
Reference voltages for the resistor ladder; see
Table 7
V
RB
voltage on pin RB 1.1 1.2 - V
V
RT
voltage on pin RT V
RT
≤ V
DDA
2.7 3.3 V
DDA
V
V
ref(dif)
differential reference
voltage
V
RT
− V
RB
1.5 2.1 2.7 V
I
ref
reference current - 0.95 - mA
R
lad
ladder resistance - 2.2 - kΩ
TC
Rlad
ladder resistor
temperature coefficient
- 4092 - mΩ/K
V
offset
offset voltage BOTTOM
[2]
- 170 - mV
TOP
[2]
- 170 - mV
V
i(a)(p-p)
peak-to-peak analog
input voltage
[3]
1.4 1.76 2.4 V
Table 6. Characteristics
…continued
V
DDA
=V5toV6=3.3V;V
DDD
=V3toV4=3.3V;V
DDO
= V20 to V11 = 3.3 V; V
SSA
,V
SSD
and V
SSO
shorted together; V
i(a)(p-p)
= 1.84 V; C
L
= 20 pF; T
amb
= 0
°
C to 70
°
C; typical values measured at T
amb
= 25
°
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

ADC0801S040/DB

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Manufacturer:
NXP Semiconductors
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