Data Sheet AD650
Rev. E | Page 9 of 20
If the approximate amount of noise that appears on C
INT
is known
(V
NOISE
), then the value of C
INT
can be checked using the following
inequality:
NOISES
OS
INT
VV
At
C
V3
101
3
(8)
For example, consider an application calling for a maximum
frequency of 75 kHz, a 0 V to 1 V signal range, and supply
voltages of only ±9 V. The component selection guide of Figure 9
is used to select 2.0 kΩ for R
IN
and 1000 pF for C
OS
. This results
in a one-shot time period of approximately 7 μs. Substituting
75 kHz into Equation 7 yields a value of 1300 pF for C
INT
. When
the input signal is near zero, 1 mA flows through the integration
capacitor to the switched current sink during the reset phase,
causing the voltage across C
INT
to increase by approximately 5.5 V.
Because the integrator output stage requires approximately 3 V
headroom for proper operation, only 0.5 V margin remains for
integrating extraneous noise on the signal line. A negative noise
pulse at this time could saturate the integrator, causing an error
in signal integration. Increasing C
INT
to 1500 pF or 2000 pF
provides much more noise margin, thereby eliminating this
potential trouble spot.
1MHz
100kHz
10kHz
50 100 1000
FREQUENCY FULL-SCALE
C
OS
(pF)
00797-008
INPUT
RESISTOR
16.9k
20k
40.2k
100k
Figure 9. Full-Scale Frequency vs. C
OS
100
20
50 100 1000
TYPICAL NONLINEARITY (ppm)
ONE SHOT CAPACITOR
C
OS
(pF)
1000
INPUT
RESISTOR
16.9k
40.2k
100k
20k
00797-009
Figure 10. Typical Nonlinearity vs. C
OS
AD650 Data Sheet
Rev. E | Page 10 of 20
BIPOLAR V/F
Figure 11 shows how the internal bipolar current sink is used to
provide a half-scale offset for a ±5 V signal range, while providing
a 100 kHz maximum output frequency. The nominally 0.5 mA
(±10%) offset current sink is enabled when a 1.24 kΩ resistor is
connected between Pin 4 and Pin 5. Thus, with the grounded
10 kΩ nominal resistance shown, a −5 V offset is developed at
Pin 2. Because Pin 3 must also be at −5 V, the current through R
IN
is 10 V/40 kΩ = +0.25 mA at V
IN
= +5 V, and 0 mA at V
IN
= –5 V.
Components are selected using the same guidelines outlined for
the unipolar configuration with one alteration. The voltage
across the total signal range must be equated to the maximum
input voltage in the unipolar configuration. In other words, the
value of the input resistor R
IN
is determined by the input voltage
span, not the maximum input voltage. A diode from Pin 1 to
ground is also recommended. This is further discussed in the
Other Circuit Considerations section.
As in the unipolar circuit, R
IN
and C
OS
must have low temperature
coefficients to minimize the overall gain drift. The 1.24 kΩ
resistor used to activate the 0.5 mA offset current should also
have a low temperature coefficient. The bipolar offset current
has a temperature coefficient of approximately −200 ppm/°C.
UNIPOLAR V/F, NEGATIVE INPUT VOLTAGE
Figure 12 shows the connection diagram for V/F conversion of
negative input voltages. In this configuration, full-scale output
frequency occurs at negative full-scale input, and zero output
frequency corresponds with zero input voltage.
A very high impedance signal source can be used because it only
drives the noninverting integrator input. Typical input impedance
at this terminal is 1 GΩ or higher. For V/F conversion of positive
input signals using the connection diagram of Figure 4, the
signal generator must be able to source the integration current
to drive the AD650. For the negative V/F conversion circuit of
Figure 12, the integration current is drawn from ground
through R1 and R3, and the active input is high impedance.
Circuit operation for negative input voltages is very similar to
positive input unipolar conversion described in the Unipolar
Configuration section. For best operating results use Equation 7
and Equation 8 in the Component Selection section.
F/V CONVERSION
The AD650 also makes a very linear frequency-to-voltage
converter. Figure 13 shows the connection diagram for F/V
conversion with TTL input logic levels. Each time the input
signal crosses the comparator threshold going negative, the one
shot is activated and switches 1 mA into the integrator input for
a measured time period (determined by C
OS
). As the frequency
increases, the amount of charge injected into the integration
capacitor increases proportionately. The voltage across the
integration capacitor is stabilized when the leakage current
through R1 and R3 equals the average current being switched
into the integrator. The net result of these two effects is an
average output voltage that is proportional to the input
frequency. Optimum performance can be obtained by selecting
components using the same guidelines and equations listed in
the Bipolar V/F section.
For a more complete description of this application, refer to
Analog Devices’ Application Note AN-279.
HIGH FREQUENCY OPERATION
Proper RF techniques must be observed when operating the
AD650 at or near its maximum frequency of 1 MHz. Lead
lengths must be kept as short as possible, especially on the one
shot and integration capacitors, and at the integrator summing
junction. In addition, at maximum output frequencies above
500 kHz, a 3.6 kΩ pull-down resistor from Pin 1 to −V
S
is
required (see Figure 14). The additional current drawn through
the pulldown resistor reduces the op amps output impedance
and improves its transient response.
00797-012
OP
AMP
COMP
IN
FREQ
OUT
OUT
ONE
SHOT
8
9
10
11
13
12
7
6
5
4
3
2
1 14
INPUT
OFFSET
TRIM
–0.6V
AD650
–V
S
–V
S
1mA
S1
C
OS
330pF
–15V
0.1µF
V
IN
±5
V
1.24k
R3
37.4k
10k
R1
5k
C
INT
1000pF
20k
250k
0.1µF
1µF
1k
+15V
+5V
DIGITAL
GND
ANALOG
GND
F
OUT
Figure 11. Connections for ±5 V Bipolar V/F with 0 kHz to 100 kHz TTL Output
Data Sheet AD650
Rev. E | Page 11 of 20
00797-013
OP
AMP
COMP
IN
FREQ
OUT
OUT
ONE
SHOT
8
9
10
11
13
12
7
6
5
4
3
2
1 14
INPUT
OFFSET
TRIM
–0.6V
AD650
–V
S
–V
S
1mA
S1
C
OS
–15V
0.1µF
–V
IN
R1
R3
C
INT
20k
250k
0.1µF
1µF
R2
+15V
+V
LOGIC
DIGITAL
GND
ANALOG
GND
F
OUT
Figure 12. Connection Diagram for V/F Conversion, Negative Input Voltage
00797-014
OP
AMP
COMP
IN
FREQ
OUT
OUT
ONE
SHOT
8
9
10
11
13
12
7
6
5
4
3
2
1 14
INPUT
OFFSET
TRIM
–0.6V
AD650
–V
S
–V
S
1mA
S1
C
OS
–15V
0.1µF
20k
250k
0.1µF
+15V
V
OUT
+5V
ANALOG
GND
F
IN
2k
500
500
560pF
R1
R3
C
INT
1N914
Figure 13. Connection Diagram for F/V Conversion
00797-015
OP
AMP
COMP
IN
FREQ
OUT
OUT
ONE
SHOT
8
9
10
11
13
12
7
6
5
4
3
2
1 14
INPUT
OFFSET
TRIM
–0.6V
AD650
–V
S
–V
S
1mA
S1
51pF
–15V
0.1µF
1000pF
20k
250k
510
0.1µF
+15V
OFFSET
ADJUST
ANALOG
GND PLANE
DIGITAL
GND
F
OUT
0MHz TO 1MHz
+5V
1µF
3.6k
14.3k
V
IN
0V TO 10V
GAIN
ADJUST
5k
Figure 14. 1 MHz V/F Connection Diagram

AD650JNZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Voltage to Frequency & Frequency to Voltage IC V/F CONVERTER
Lifecycle:
New from this manufacturer.
Delivery:
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