Data Sheet AD650
Rev. E | Page 13 of 20
Other circuit components do not directly influence the accuracy
of the VFC over temperature changes as long as their actual
values are not as different from the nominal value as to preclude
operation. This includes the integration capacitor C
INT
. A change
in the capacitance value of C
INT
simply results in a different rate of
voltage change across the capacitor. During the integration phase
(see Figure 8), the rate of voltage change across C
INT
has the
opposite effect that it does during the reset phase. The result is
that the conversion accuracy is unchanged by either drift or
tolerance of C
INT
. The net effect of a change in the integrator
capacitor is simply to change the peak-to-peak amplitude of the
sawtooth waveform at the output of the integrator.
The gain temperature coefficient of the AD650 is not a constant
value. Rather, the gain TC is a function of both the full-scale
frequency and the ambient temperature. At a low full-scale
frequency, the gain TC is determined primarily by the stability of
the internal reference (a buried Zener reference). This low speed
gain TC can be quite effective; at 10 kHz full scale, the gain TC near
25°C is typically 0 ± 50 ppm/°C. Although the gain TC changes
with ambient temperature (tending to be more positive at higher
temperatures), the drift remains within a ±75 ppm/°C window over
the entire military temperature range. At full-scale frequencies
higher than 10 kHz, dynamic errors become much more important
than the static drift of the dc reference. At a full-scale frequency
of 100 kHz and above, these timing errors dominate the gain
TC. For example, at 100 kHz full-scale frequency (R
IN
= 40 kΩ and
C
OS
= 330 pF) the gain TC near room temperature is typically
−80 ±50 ppm/°C, but at an ambient temperature near 125°C, the
gain TC tends to be more positive and is typically 15 ±50 ppm/°C.
This information is presented in a graphical form in Figure 15.
The gain TC always tends to become more positive at higher
temperatures. Therefore, it is possible to adjust the gain TC of
the AD650 by using a one-shot capacitor with an appropriate
TC to cancel the drift of the circuit. For example, consider the
100 kHz full-scale frequency. An average drift of −100 ppm/°C
means that as temperature is increased, the circuit produces a
lower frequency in response to a given input voltage. This means
that the one-shot capacitor must decrease in value as temperature
increases in order to compensate the gain TC of the AD650; that
is, the capacitor must have a TC of −100 ppm/°C. Now consider
the 1 MHz full-scale frequency.
100
–50
10kHz
100kHz
1MHz
–25 0 25 50
75
100 125
0
–100
–200
–300
–400
TEMPERATURE (°C)
GAIN TC (ppm/°C)
00797-016
Figure 15. Gain TC vs. Temperature
It is not possible to achieve much improvement in performance
unless the expected ambient temperature range is known. For
example, in a constant low temperature application such as
gathering data in an Arctic climate (approximately −20°C), a
C
OS
with a drift of −310 ppm/°C is called for in order to compensate
the gain drift of the AD650. However, if that circuit should see
an ambient temperature of 75°C, then the C
OS
capacitor would
change the gain TC from approximately 0 ppm to 310 ppm/°C.
The temperature effects of these components are the same when
the AD650 is configured for negative or bipolar input voltages,
and for F/V conversion as well.
NONLINEARITY SPECIFICATION
The linearity error of the AD650 is specified by the endpoint
method. That is, the error is expressed in terms of the deviation
from the ideal voltage to frequency transfer relation after
calibrating the converter at full scale and zero. The nonlinearity
varies with the choice of one-shot capacitor and input resistor
(see Figure 10). Verification of the linearity specification
requires the availability of a switchable voltage source (or a
DAC) having a linearity error below 20 ppm, and the use of
very long measurement intervals to minimize count
uncertainties. Every AD650 is automatically tested for linearity,
and it is not usually necessary to perform this verification,
which is both tedious and time consuming. If it is required to
perform a nonlinearity test either as part of an incoming quality
screening or as a final product evaluation, an automated bench-
top tester proves useful. Such a system based on Analog
Devices’ LTS-2010 is described in “V-F Converters Demand
Accurate Linearity Testing,” by L. DeVito, (Electronic Design,
March 4, 1982).
The voltage-to-frequency transfer relation is shown in Figure 16
and Figure 17 with the nonlinearity exaggerated for clarity. The
first step in determining nonlinearity is to connect the endpoints of
the operating range (typically at 10 mV and 10 V) with a straight
line. This straight line is then the ideal relationship that is desired
from the circuit. The second step is to find the difference between
this line and the actual response of the circuit at a few points
between the endpoints—typically ten intermediate points
suffices. The difference between the actual and the ideal
response is a frequency error measured in hertz. Finally, these
frequency errors are normalized to the full-scale frequency and
expressed either as parts per million of full scale (ppm) or parts
per hundred of full scale (%). For example, on a 100 kHz full
scale, if the maximum frequency error is 5 Hz, the nonlinearity
is specified as 50 ppm or 0.005%. Typically on the 100 kHz
scale, the nonlinearity is positive and the maximum value
occurs at about midscale (Figure 16). At higher full-scale
frequencies, (500 kHz to 1 MHz), the nonlinearity becomes “S”
shaped and the maximum value can be either positive or negative.
Typically, on the 1 MHz scale (R
IN
= 16.9 kΩ, C
OS
= 51 pF) the
nonlinearity is positive below about 2/3 scale and is negative
above this point. This is shown graphically in Figure 17.
