Data Sheet AD650
Rev. E | Page 15 of 20
A second major difference is that the output only sinks 1 mA to
the negative supply. There is no pulldown stage at the output
other than the 1 mA current source used for the V-to-F
conversion. The op amp sources a great deal of current from the
positive supply, and it is internally protected by current limiting.
The output of the op amp can be driven to within 3 V of the
positive supply when it is not sourcing external current. When
sourcing 10 mA the output voltage can be driven to within 6 V
of the positive supply.
A third difference between this op amp and a normal device is
that the inverting input, Pin 3, is bias current compensated and
the noninverting input is not bias-current compensated. The
bias current at the inverting input is nominally zero, but can be
as much as 20 nA in either direction. The noninverting input
typically has a bias current of 40 nA that always flows into the
node (an npn input transistor). Therefore, it is not possible to
match input voltage drops due to bias currents by matching
input resistors.
The op amp has provisions for trimming the input offset
voltage. A potentiometer of 20 kΩ is connected from Pin 13 to
Pin 14 and the wiper is connected to the positive supply
through a 250 kΩ resistor. A potential of about 0.6 V is
established across the 250 kΩ resistor, and the 3 μA current is
injected into the null pins. It is also possible to null the op amp
offset voltage by using only one of the null pins and by using a
bipolar current either into or out of the null pin. The amount of
current required is very smalltypically less than 3 μA. This
technique is shown in the Applications section of this data
sheet; the autozero circuit uses this technique.
The bipolar offset current is activated by connecting a 1.24 kΩ
resistor between Pin 4 and the negative supply. The resulting
current delivered to the op amp noninverting input is nominally
0.5 mA and has a tolerance of ±10%. This current is then used
to provide an offset voltage when Pin 2 is tied to ground through
a resistor. The 0.5 mA that appears at Pin 2 is also flowing
through the 1.24 kΩ resistor. An external resistor is used to
activate the bipolar offset current source to provide the lowest
tolerance and temperature drift of the resulting offset voltage.
It is possible to use other values of resistance between Pin 4 and
−V
S
to obtain a bipolar offset current different from 0.5 mA.
Figure 19 shows the relationship between the bipolar offset
current and the value of the resistor used to activate the source.
µA
200
500 4000
EXTERNAL RESISTOR
BIPOLAR OFFSET CURRENT
400
600
800
1000
1000 1500 2000 2500 3000 3500
00797-020
Figure 19. Bipolar Offset Current vs. External Resistor
AD650 Data Sheet
Rev. E | Page 16 of 20
APPLICATIONS
DIFFERENTIAL VOLTAGE-TO-FREQUENCY
CONVERSION
The circuit in Figure 20 accepts a true floating differential input
signal. The common-mode input, V
CM
, can be in the range
+15 V to −5 V with respect to analog ground. The signal input,
V
IN
, can be ±5 V with respect to the common-mode input. Both
inputs are low impedance; the source that drives the common-
mode input must supply the 0.5 mA drawn by the bipolar offset
current source, and the source that drives the signal input must
supply the integration current.
If less common-mode voltage range is required, then a lower
voltage Zener can be used. For example, if a 5 V Zener is used,
the V
CM
input can be in the range +10 V to −5 V. If the Zener is
not used at all, the common-mode range is ±5 V with respect to
analog ground. If no Zener is used, the 10 kΩ pulldown resistor
is not needed and the integrator output (Pin 1) is connected
directly to the comparator input (Pin 9).
AUTOZERO CIRCUIT
In order to exploit the full dynamic range of the AD650 VFC,
very small input voltages need to be converted. For example, a
six decade dynamic range based on a full scale of 10 V requires
accurate measurement of signals down to 10 μV. In these
situations, a well-controlled input offset voltage is imperative. A
constant offset voltage does not affect dynamic range but simply
shifts all of the frequency readings by a few hertz. However, if
the offset should change, it is not possible to distinguish
between a small change in a small input voltage and a drift of
the offset voltage. Therefore, the usable dynamic range is less.
The circuit shown in Figure 21 provides automatic adjustment
of the op amp offset voltage. The circuit uses an AD582 sample-
and-hold amplifier to control the offset, and the input voltage to
the VFC is switched between ground and the signal to be
measured via an AD7512DI analog switch. The offset of the
AD650 is adjusted by injecting a current into—or drawing a
current out of—Pin 13. Note that only one of the offset null pins
is used. During the VFC norm mode, the SHA is in the hold
mode and the hold capacitor is very large, 0.1 μF, which holds
the AD650 offset constant for a long period of time.
When the circuit is in the autozero mode, the SHA is in sample
mode and behaves like an op amp. The circuit is a variation of
the classical two amplifier servo loop, where the output of the
device under test (DUT)—here the DUT is the AD650 op
amp—is forced to ground by the feedback action of the control
amplifier—the SHA. Because the input of the VFC circuit is
connected to ground during the autozero mode, the input
current that can flow is determined by the offset voltage of the
AD650 op amp. Because the output of the integrator stage is
forced to ground, it is known that the voltage is not changing (it
is equal to ground potential). Therefore, if the output of the
integrator is constant, its input current must be zero, so the
offset voltage has been forced to be zero. Note that the output of
the DUT could have been forced to any convenient voltage
other than ground. All that is required is that the output voltage
be known to be constant. Note also that the effect of the bias
current at the inverting input of the AD650 op amp is also
mulled in this circuit. The 1000 pF capacitor shunting the
200 kΩ resistor is compensation for the two amplifier servo
loop. Two integrators in a loop require a single zero for
compensation. The 3.6 kΩ resistor from Pin 1 of the AD650 to
the negative supply is not part of the autozero circuit, but rather,
it is required for VFC operation at 1 MHz.
00797-021
OP
AMP
COMP
IN
FREQ
OUT
OUT
ONE
SHOT
8
9
10
11
13
12
7
6
5
4
3
2
1 14
INPUT
OFFSET
TRIM
10V ZENER 1N5240
NOTES
1. V
CM
IS THE COMMON MODE INPUT +15V TO –5V WITH RESPECT TO ANALOG GROUND.
2. V
IN
IS THE SIGNAL INPUT ±5V WITH RESPECT TO V
CM
.
–0.6V
AD650
–V
S
V
IN
V
CM
INPU
T
–V
S
1mA
S1
20k
250k
0.1µF
1µF
+15V
GND
GND
FREQUENCY
OUTPUT
0kHz TO 100kHz
–15V
+5V
+
+
0.1µF
+
1k
10k
C
OS
330pF
C
I
1000pF
1.24k
40k
10k
Figure 20. Differential Input
Data Sheet AD650
Rev. E | Page 17 of 20
PHASE-LOCKED LOOP F/V CONVERSION
Although the F/V conversion technique shown in Figure 13 is
quite accurate and uses only a few extra components, it is very
limited in terms of signal frequency response and carrier feed-
through. If the carrier (or input) frequency changes
instantaneously, then the output cannot change very rapidly due
to the integrator time constant formed by C
INT
and R
IN
. While it
is possible to decrease the integrator time constant to provide
faster settling of the F-to-V output voltage, the carrier
feedthrough then becomes larger. For signal frequency response
in excess of 2 kHz, a phase-locked F/V conversion technique
such as the one shown in Figure 22 is recommended.
In a phase-locked loop circuit, the oscillator is driven to a
frequency and phase equal to an input reference signal. In
applications such as a synthesizer, the oscillator output
frequency is first processed through a programmable “divide by
N” before being applied to the phase detector as feedback. Here
the oscillator frequency is forced to be equal to “N times” the
reference frequency. It is this frequency output that is the
desired output signal and not a voltage. In this case, the AD650
offers compact size and wide dynamic range.
14 13 1
8
6
54
2
3
7
9
10
1
2
5
4
3
6
+V
S
–V
S
+V
S
AD582
–V
S
1000pF
CAP
0.1µF
200k
10k
OUTPUT
1k
1
2
3
4
14
13
12
11
5 10
6 9
7 8
AD7512
–V
S
+V
S
CONTROL
INPUT
+5V
INPUT
VOLTAGE
16.9k
0.5mA
BIPOLAR
OFFSET
1mA
–V
S
+IN
–IN
+V
S
C
OS
NULL
AD650
NULL
COMPARATOR
INPUT
COMPARATOR
FREQUENCY
OUTPUT
DIGITAL
GND
ANALOG
GND
FREQUENCY
OUTPUT
ONE
SHOT
OP
AMP
–0.6 VOLT
500
10µF
0.1µF 51pF
0.1µF
+
10
–15V +15V GND
1000pF
9
00797-022
3.6k
–5 VOLTS VFC NORMAL
GND AUTO ZERO
1112
8
Figure 21. Autozero Circuit
C
51pF
15pF
R
140k
71.5k
590k
–15V
1012
4 12
11
3
13
9
5
AD650
1MHz FULL-SCALE
R
IN
= 16.9k
C
OS
= 51pF
C
INT
= 1000pF
(UNIPOLAR INPUT)
FREQ
OUT
INPUT
CARRIER
VOLTS INPUT
TO AD650
NAND XOR
1
2
5
4
36
G
D
B
S
1/2 7474
1/2 7474
D
1
PR
1
D
2
PR
2
Q
1
Q
2
CLEAR
1
SD211
DMOSFET
D TYPE FLIP FLOP
1
1
F/V
VOLTAGE
OUTPUT
INPUT
CARRIER
CLOCK
1
CLOCK
2
CLEAR
2
00797-023
AD509
OP AMP
1/4 7400
7486
Figure 22. Phase-Locked Loop F/V Conversion

AD650JNZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Voltage to Frequency & Frequency to Voltage IC V/F CONVERTER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union