3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
DESCRIPTION:
The IDT72T2098/72T20108/72T20118/72T20128 are exceptionally deep,
extremely high speed, CMOS First-In-First-Out (FIFO) memories with the ability
to read and write data on both rising and falling edges of clock. The device has
a flexible x20/x10 Bus-Matching mode and the option to select Single or Double
Data clock rates for input and output ports. These FIFOs offer several key user
benefits:
• Flexible x20/x10 Bus-Matching on both read and write ports
• Ability to read and write on both rising and falling edges of a clock
• User selectable Single or Double Data Rate of input and output ports
• A user selectable MARK location for retransmit
• User selectable I/O structure for HSTL or LVTTL
• The first word data latency period, from the time the first word is written to
an empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 5Mbit
• 5Gbps throughput
Bus-Matching Double Data Rate FIFOs are particularly appropriate for
network, video, telecommunications, data communications and other applica-
tions that require fast data transfer on both rising and falling edges of the clock.
This is a great alternative to increasing data rate without extending the width of
the bus or the speed of the device. They are also effective in applications that
need to buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
which can assume either a 20-bit or a 10-bit width as determined by the state
of external control pins Input Width (IW), Output Width (OW) during the Master
Reset cycle.
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
(WEN) input. Data present on the Dn data inputs can be written into the FIFO
on every rising and falling edge of WCLK when WEN is asserted and Write
Single Data Rate (WSDR) pin held HIGH. Data can be selected to write only
on the rising edges of WCLK if WSDR is asserted. To guarantee functionality
of the device, WEN must be a controlled signal and not tied to ground. This is
important because WEN must be HIGH during the time when the Master Reset
(MRS) pulse is LOW. In addition, the WSDR pin must be tied HIGH or LOW.
It is not a controlled signal and cannot be changed during FIFO operation.
Write operations can be selected for either Single or Double Data Rate mode.
For Single Data Rate operation, writing into the FIFO requires the Write Single
Data Rate (WSDR) pin to be asserted. Data will be written into the FIFO on the
rising edge of WCLK when the Write Enable (WEN) is asserted. For Double
Data Rate operations, writing into the FIFO requires WSDR to be deasserted.
Data will be written into the FIFO on both rising and falling edge of WCLK when
WEN is asserted.
The output port is controlled by a Read Clock (RCLK) input and a Read
Enable (REN) input. Data is read from the FIFO on every rising and falling edge
of RCLK when REN is asserted and Read Single Data Rate (RSDR) pin held
HIGH. Data can be selected to read only on the rising edges of RCLK if RSDR
is asserted. To guarantee functionality of the device, REN must be a controlled
signal and not tied to ground. This is important because REN must be HIGH
during the time when the Master Reset (MRS) pulse is LOW. In addition, the
RSDR pin must be tied HIGH or LOW. It is not a controlled signal and cannot
be changed during FIFO operation.
Read operations can be selected for either Single or Double Data Rate mode.
Similar to the write operations, reading from the FIFO in single data rate requires
the Read Single Data Rate (RSDR) pin to be asserted. Data will be read from
the FIFO on the rising edge of RCLK when the Read Enable (REN) is asserted.
For Double Data Rate operations, reading into the FIFO requires RSDR to be
deasserted. Data will be read out of the FIFO on both rising and falling edge
of RCLK when and REN is asserted.
Both the input and output port can be selected for either 2.5V LVTTL or HSTL
operation. This can be achieved by tying the HSTL signal LOW for LVTTL or
HIGH for HSTL voltage operation. When the read port is setup for HSTL mode,
the Read Chip Select (RCS) input also has the benefit of disabling the read port
inputs, providing additional power savings.
There is the option of selecting different data rates on the input and output ports
of the device. There are a total of four combinations to choose from, Double Data
Rate to Double Data Rate (DDR to DDR), DDR to Single Data Rate (DDR to
SDR), SDR to DDR, and SDR to SDR. The clocking can be set up using the
WSDR and RSDR pins. For example, to set up the input to output combination
of DDR to SDR, WSDR will be HIGH and RSDR will be LOW. Read and write
operations are initiated on the rising edge of RCLK and WCLK respectively,
never on the falling edge. If REN or WEN is asserted after a rising edge of clock,
no read or write operations will be possible on the falling edge of that same pulse.
An Output Enable (OE) input is provided for high-impedance control of the
outputs. A read Chip Select (RCS) input is also provided for synchronous
enable/disable of the read port control input, REN. The RCS input is synchro-
nized to the read clock, and also provides high-impedance controls to the Qn
data outputs. When RCS is disabled, REN will be disabled internally and the
data outputs will be in High-Impedance. Unlike the Read Chip Select signal
however, OE is not synchronous to RCLK. Outputs are high-impedance shortly
after a delay time when the OE transitions from LOW to HIGH.
The Echo Read Enable (EREN) and Echo Read Clock (ERCLK) outputs
are used to provide tighter synchronization between the data being transmitted
from the Qn outputs and the data being received by the input device. These
output signals from the read port are required for high-speed data communi-
cations. Data read from the read port is available on the output bus with respect
to EREN and ERCLK, which is useful when data is being read at high-speed
operations where synchronization is important.
The frequencies of both the RCLK and WCLK signals may vary from 0 to fMAX
with complete independence. There are no restrictions on the frequency of one
clock input with respect to another.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines. Be aware that
in Double Data Rate (DDR) mode only the IDT Standard mode is available.
In FWFT mode, the first word written to an empty FIFO is clocked directly to
the data output lines after three transitions of RCLK. A read operation does not
have to be performed to access the first word written to the FIFO. However,
subsequent words written to the FIFO do require a LOW on REN for access.
The state of the FWFT input during Master Reset determines the timing mode
in use.
For applications requiring more data storage capacity than a single FIFO can
provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have four flag pins, EF/OR (Empty Flag or Output Ready), FF/
IR (Full Flag or Input Ready), PAE (Programmable Almost-Empty flag), and
PAF (Programmable Almost-Full flag). The EF and FF functions are selected
in IDT Standard mode. The IR and OR functions are selected in FWFT mode.
PAE and PAF are always available for use, irrespective of timing mode.
PAE and PAF flags can be programmed independently to switch at any point
in memory. Programmable offsets mark the location within the internal memory
that activates the PAE and PAF flags and can only be programmed serially. To
program the offsets, set SEN active and data can be loaded via the Serial Input
