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IDT72T20118L5BB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
43
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
Figure 23 . Retransmit from MARK in Double Data Rate Mode (IDT Standard Mode)
NOTES:
1. Retransmit setup is complete when EF returns HIGH.
2. OE = LOW;RCS = LOW.
3. RT must be HIGH when reading from FIFO.
4. Once MARK is set, the write pointer will not increment past the ‘marked’ location, preventing overwrites of Retransmit data.
5. Before a “MARK” can be set there must be at least 160 bytes of data between the Write Pointer and Read Pointer locations. (160 bytes = 16 words = 8 long words).
6. RCLK must be free running for EF to update.
7. A transition in the PAE flag may not occur until one RCLK cycle later than shown.
8. In DDR mode the MARK function will “MARK” words only on even word boundaries (i.e. Rising edge of RCLK).
Q
0-
Qn
WCLK
RCLK
REN
PAF
t
CLKL2
t
CLKH2
t
CLK2
t
A
W
MK
MARK
t
A
t
A
t
A
W
MK+2
t
A
t
A
W
MK+3
W
MK+4
W
MK+5
W
MK+6
W
MK+n
RT
EF
PAE
t
ENS
t
ENH
t
REF
t
REF
t
ENS
1
2
t
A
t
A
t
A
t
A
W
MK
W
MK+1
W
MK+2
t
SKEW2
1
2
5996 drw26
t
ENH
t
ENS
t
ENS
t
PAES
(7)
t
PAFS
W
MK+1
44
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
Figure 24. Retransmit from Mark (FWFT Mode)
NOTES:
1. Retransmit setup is complete when OR returns LOW.
2. OE = LOW;RCS = LOW.
3. RT must be HIGH when reading from FIFO.
4. Once MARK is set, the write pointer will not increment past the ‘marked’ location, preventing overwrites of Retransmit data.
5. Before a “MARK” can be set there must be at least 160 bytes of data between the Write Pointer and Read Pointer locations. (160 bytes = 16 words = 8 long words).
6. RCLK must be free running for EF to update.
7. A transition in the PAE flag may not occur until one RCLK cycle later than shown.
t
REF
t
ENS
t
ENH
5996 drw27
t
ENS
W
MK-1
WCLK
RCLK
REN
RT
OR
PAF
PAE
Q
n
12
1
t
PAFS
t
REF
2
WEN
t
ENS
t
A
t
ENS
W
MK
W
MK+1
t
A
t
A
W
MK+n
t
A
W
MK+1
W
MK+2
t
A
t
ENS
MARK
t
ENH
t
ENS
t
PAES
(7)
t
A
t
SKEW2
W
MK
t
A
45
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
Figure 25. Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. In SDR mode, X = 16 for the IDT72T2098, X = 17 for the IDT72T20108, X = 18 for the IDT72T20118, X = 19 for the IDT72T20128 for X10 mode. X = 15 for the IDT72T2098,
X = 16 for the IDT72T20108, X = 17 for the IDT72T20118, X = 18 for the IDT72T20128 for all other modes.
2. In DDR mode, X = 15 for the IDT72T2098, X = 16 for the IDT72T20108, X = 17 for the IDT72T20118, X = 18 for the IDT72T20128 for X10 to X10 mode. X = 14 for the IDT72T2098,
X = 15 for the IDT72T20108, X = 16 for the IDT72T20118, X = 17 for the IDT 72T20128 for all other modes.
SCLK
SEN
SI
5996 drw28
EMPTY OFFSET
FULL OFFSET
BIT X
(1)
t
SENS
t
SDS
t
SENH
BIT X
(1)
BIT 1
t
ENH
t
SDH
t
SCLK
t
SCKH
t
SCKL
BIT 1
Figure 26. Reading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. In SDR mode, X = 15 for the IDT72T2098, X = 17 for the IDT72T20108, X = 18 for the IDT72T20118, X = 19 for the IDT72T20128 for X10 mode. X = 15 for the IDT72T2098,
X = 16 for the IDT72T20108, X = 17 for the IDT20118, X = 18 for the IDT72T20128 for all other modes.
2. In DDR mode, X = 15 for the IDT72T2098, X = 16 for the IDT72T20108, X = 17 for the IDT72T20118, X = 18 for the IDT20128, for X10 to X10 mode. X = 14 for the IDT72T72098,
X = 15 for the IDT72T20108, X = 16 for the IDT72T20118, X = 17 for the IDT72T20128 for all other modes.
3. Offset register values are always read starting from the first location in the offset register upon initiating SREN.
SCLK
SREN
SO
5996 drw29
BIT 0
EMPTY OFFSET
FULL OFFSET
BIT X
(1)
t
SENS
t
SOA
t
SENH
BIT X
(1)
t
ENH
t
SOA
t
SCLK
t
SCKH
t
SCKL
BIT 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

IDT72T20118L5BB

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IC FIFO 65536X20 5NS 208BGA
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