22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
TABLE 7 — BUS-MATCHING WRITE TO READ RATIO (CONTINUED)
ONE WRITE TO FOUR READ (1:4)
x20 DDR Input to x10 SDR Output
DDR Write Clock x20 Data In SDR Read Clock x10 Data Out
Positive Edge 1 D[19:10] <= B1 Positive Edge 1 Q[9:0] <= B1
Positive Edge 1 D[9:0] <= B2 Positive Edge 2 Q[9:0] <= B2
Negative Edge 1 D[19:10] <= B3 Positive Edge 3 Q[9:0] <= B3
Negative Edge 1 D[9:0] <= B4 Positive Edge 4 Q[9:0] <= B4
TWO WRITE TO ONE READ (2:1)
x20 SDR Input to x20 DDR Output
SDR Write Clock x20 Data In DDR Read Clock x20 Data Out
Positive Edge 1 D[19:0] <= W1 Positive Edge 1 Q[19:0] <= W1
Positive Edge 2 D[19:0] <= W2 Negative Edge 1 Q[19:0] <= W2
x10 DDR Input to x20 DDR Output
DDR Write Clock x10 Data In DDR Read Clock x20 Data Out
Positive Edge 1 D[9:0] <= B1 Positive Edge 1 Q[19:10] <= B1
Negative Edge 1 D[9:0] <= B2 Postive Edge 1 Q[9:0] <= B2
Positive Edge 2 D[9:0] <= B3 Negative Edge 1 Q[19:10] <= B3
Negative Edge 2 D[9:0] <= B4 Negative Edge 1 Q[9:0] <= B4
x10 SDR Input to x20 SDR Output
SDR Write Clock x10 Data In SDR Read Clock x20 Data Out
Positive Edge 1 D[19:10] <= B1 Positive Edge 1 Q[19:10] <= B1
Positive Edge 2 D[9:0] <= B2 Positive Edge 1 Q[9:0] <= B2
x10 SDR Input to x10 DDR Output
DDR Write Clock x10 Data In SDR Read Clock x10 Data Out
Positive Edge 1 D[9:0] <= B1 Positive Edge 1 Q[9:0] <= B1
Positive Edge 2 D[9:0] <= B3 Negative Edge 1 Q[9:0] <= B3
Configuration
WSDR RSDR IW OW
HLLL
FOUR WRITE TO ONE READ (4:1)
x10 SDR Input to x20 DDR Output
SDR Write Clock x10 Data In DDR Read Clock x20 Data Out
Positive Edge 1 D[9:0] <= B1 Positive Edge 1 Q[19:10] <= B1
Positive Edge 2 D[9:0] <= B2 Positive Edge 1 Q[9:0] <= B2
Positive Edge 3 D[9:0] <= B3 Negative Edge 1 Q[19:0] <= B3
Positive Edge 4 D[9:0] <= B4 Negative Edge 1 Q[9:0] <= B4
Configuration
WSDR RSDR IW OW
LHLL
Configuration
WSDR RSDR IW OW
HHHL
Configuration
WSDR RSDR IW OW
LLHL
Configuration
WSDR RSDR IW OW
LHHH
Configuration
WSDR RSDR IW OW
LHHL
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
TABLE 8 — TSKEW MEASUREMENT
Data Port Status Flags TSKEW Measurement
Configuration
DDR Input EF & PAE Negative Edge WCLK to
to Positive Edge RCLK
DDR Output
FF & PAF Negative Edge RCLK to
Positive Edge WCLK
DDR Input EF & PAE Negative Edge WCLK to
to Positive Edge RCLK
SDR Output
FF & PAF Positive Edge RCLK to
Positive Edge WCLK
SDR Input EF & PAE Positive Edge WCLK to
to Positive Edge RCLK
DDR Output
FF & PAF Negative Edge RCLK to
Positive Edge WCLK
SDR Input EF & PAE Positive Edge WCLK to
to Positive Edge RCLK
SDR Output
FF & PAF Positive Edge RCLK to
Positive Edge WCLK
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
Figure 5. Standard JTAG Timing
SYSTEM INTERFACE PARAMETERS
Parameter Symbol Test
Conditions
Min. Max. Units
JTAG Clock Input Period tTCK - 100 - ns
JTAG Clock HIGH tTCKHIGH -40-ns
JTAG Clock Low tTCKLOW -40-ns
JTAG Clock Rise Time tTCKRISE --5
(1)
ns
JTAG Clock Fall Time tTCKFALL --5
(1)
ns
JTAG Reset tRST -50-ns
JTAG Reset Recovery tRSR -50-ns
JTAG
AC ELECTRICAL CHARACTERISTICS
(vcc = 2.5V ± 5%; Tcase = 0°C to +85°C)
IDT72T2098
IDT72T20108
IDT72T20118
IDT72T20128
Parameter Symbol Test Conditions Min. Max. Units
Data Output tDO
(1)
-20ns
Data Output Hold tDOH
(1)
0-ns
Data Input tDS trise=3ns 10 - ns
tDH tfall=3ns 10 -
NOTE:
1. 50pf loading on external output signals.
JTAG TIMING SPECIFICATION
NOTE:
1. Guaranteed by design.
t
4
t
3
TDO
TDO
TDI/
TMS
TCK
TRST
t
DO
Notes to diagram:
t1 =
t
TCKLOW
t2 =
t
TCKHIGH
t3 =
t
TCKFALL
t4 = t
TCKRISE
t5 =
tRST
(reset pulse width)
t6 = tRSR (reset recovery)
5996 drw08
t
5
t
6
t
1
t
2
t
TCK
t
DH
t
DS

IDT72T20118L5BB

Mfr. #:
Manufacturer:
Description:
IC FIFO 65536X20 5NS 208BGA
Lifecycle:
New from this manufacturer.
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