10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)
Commercial Commercial Com’l & Ind’l
(2)
Commercial
IDT72T2098L4 IDT72T2098L5 IDT72T2098L6-7 IDT72T2098L10
IDT72T20108L4 IDT72T20108L5 IDT72T20108L6-7 IDT72T20108L10
IDT72T20118L4 IDT72T20118L5 IDT72T20118L6-7 IDT72T20118L10
IDT72T20128L4 IDT72T20128L5 IDT72T20128L6-7 IDT72T20128L10
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS1 Clock Cycle Frequency SDR — 250 — 200 — 150 — 100 MHz
fS2 Clock Cycle Frequency DDR — 110 — 100 — 75 — 50 MHz
tA Data Access Time 0.6 3.2 0.6 3.6 0.6 3.8 0.6 4.5 ns
tASO Data Access Serial Output Time 0.6 3.2 0.6 3.6 0.6 3.8 0.6 4.5 ns
tCLK1 Clock Cycle Time SDR 4 — 5 — 6.7 — 10 — ns
tCLK2 Clock Cycle Time DDR 9.1 — 10 — 13 — 20 — ns
tCLKH1 Clock High Time SDR 1.8 — 2.3 — 2.8 — 4.5 — ns
tCLKH2 Clock High Time DDR 4.0 — 4.5 — 6.0 — 9.5 — ns
tCLKL1 Clock Low Time SDR 1.8 — 2.3 — 2.8 — 4.5 — ns
tCLKL2 Clock Low Time DDR 4.0 — 4.5 — 6.0 — 9.5 — ns
tDS Data Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tDH Data Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tENS Enable Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tENH Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tWCSS WCS setup time 1.2 — 1.5 — 2.0 — 3.0 — ns
tWCSH WCS hold time 0.5 — 0.5 — 0.5 — 0.5 — ns
fC Clock Cycle Frequency (SCLK) — 10 — 10 — 10 — 10 MHz
tSCLK Serial Clock Cycle 100 — 100 — 100 — 100 — ns
tSCKH Serial Clock High 45 — 45 — 45 — 45 — ns
tSCKL Serial Clock Low 45 — 45 — 45 — 45 — ns
tSDS Serial Data In Setup 15 — 15 — 15 — 15 — ns
tSDH Serial Data In Hold 5 — 5 — 5 — 5 — ns
tSENS Serial Enable Setup 5 — 5 — 5 — 5 — ns
tSENH Serial Enable Hold 5 — 5 — 5 — 5 — ns
tRS Reset Pulse Width
(3)
30 — 30 — 30 — 30 — ns
tRSS Reset Setup Time 15 — 15 — 15 — 15 — ns
tHRSS HSTL Reset Setup Time 4 — 4 — 4 — 4 — µs
tRSR Reset Recovery Time 10 — 10 — 10 — 10 — ns
tRSF Reset to Flag and Output Time — 10 — 12 — 15 — 15 ns
tOLZ Output Enable to Output in Low Z
(4)
0—0—0—0—ns
tOE Output Enable to Output Valid — 3.2 — 3.6 — 3.8 — 4.5 ns
tOHZ Output Enable to Output in High Z
(4)
— 3.2 — 3.6 — 3.8 — 4.5 ns
tWFF Write Clock to FF or IR — 3.2 — 3.6 — 3.8 — 4.5 ns
tREF Read Clock to EF or OR — 3.2 — 3.6 — 3.8 — 4.5 ns
tPAFS Write Clock to Programmable Almost-Full Flag — 3.2 — 3.6 — 3.8 — 4.5 ns
tPAES Read Clock to Programmable Almost-Empty Flag — 3.2 — 3.6 — 3.8 — 4.5 ns
tERCLK RCLK to Echo RCLK output — 3.6 — 4 — 4.3 — 5 ns
tCLKEN RCLK to Echo REN output — 3.2 — 3.6 — 3.8 — 4.5 ns
tRCSLZ RCLK to Active from High-Z — 3.2 — 3.6 — 3.8 — 4.5 ns
tRCSHZ RCLK to High-Z
(4)
— 3.2 — 3.6 — 3.8 — 4.5 ns
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 3.5—4—5—7—ns
tSKEW2 Skew time between RCLK & WCLK for EF/OR & FF/IR in DDR mode 3.5—4—5—7—ns
tSKEW3 Skew time between RCLK and WCLK for PAE and PAF 4—5—6—8—ns
NOTES:
1. All AC timings apply to both IDT Standard mode and First Word Fall Through mode.
2. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
