34
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
Figure 14. Read Cycle, Empty Flag and First Data Word Latency in x20 DDR to x10 SDR with Bus-Matching and Rate-Matching (IDT Standard Mode)
RCLK
EF
WEN
REN
WCS
tENS
tSKEW2
(1)
D0-D19
tDS
W
0
- W
1
Q0-Q9
WCLK
tENH
twcSH
tWCSS
W
2
-
W
3
tDH
tDS
tDH
12
tREF
tENS
tA tA
tA tA
W0
W1 W2 W3
tENH
tREF
Previous Data in Ouput Register
5996 drw17
NOTES:
1. t
SKEW2 is the minimum time between a falling WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the falling edge of WCLK and the rising edge of RCLK
is less than t
SKEW2, then EF deassertion may be delayed one extra RCLK cycle.
2. REN = LOW.
3. First data word latency = t
SKEW1 + 1*tRCLK + tREF.
4. RCS = LOW, WSDR = HIGH and RSDR = HIGH.
5. RCLK must be free running for EF to update.
