DocID027271 Rev 1 13/22
STGIPN3H60-E Electrical characteristics
22
3.2 Waveform definitions
Figure 5. Dead time and interlocking waveform definitions
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
DTLH DTHL
DT
LH
DT
HL
DTLH
DTHL
DTLH
DTHL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
INTERLOCKING
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
(*) HIN and LIN can be connected together and driven by just one control signal
INTERLOCKING
INTERLOCKING
G
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
Smart shutdown function STGIPN3H60-E
14/22 DocID027271 Rev 1
4 Smart shutdown function
The STGIPN3H60-E integrates a comparator for fault sensing purposes. The comparator
non-inverting input (CIN) can be connected to an external shunt resistor in order to
implement a simple overcurrent protection function. When the comparator triggers, the
device is set in shutdown state and both its outputs are set to low-level leading the half
bridge in 3-state. In the common overcurrent protection architectures the comparator output
is usually connected to the shutdown input through a RC network, in order to provide a
mono-stable circuit, which implements a protection time that follows the fault condition. Our
smart shutdown architecture allows to immediately turn-off the output gate driver in case of
overcurrent, the fault signal has a preferential path which directly switches off the outputs.
The time delay between the fault and the outputs turn-off is no more dependent on the RC
values of the external network connected to the shutdown pin. At the same time the internal
logic turns on the open-drain output and holds it on until the shutdown voltage goes below
the logic input lower threshold. Finally the smart shutdown function provides the possibility
to increase the real disable time without increasing the constant time of the external RC
network.
DocID027271 Rev 1 15/22
STGIPN3H60-E Smart shutdown function
22
Figure 6. Smart shutdown timing waveforms
Please refer to Table 12 for internal propagation delay time details.
SD/OD
FROM/TO
CONTROLLER
V
BIAS
C
SD
R
SD
SMART
SD
LOGIC
R
ON_OD
SHUT DOWN CIRCUIT
R
PD_SD
An approximation of the disable time is given by:
where:
HIN/LIN
HVG/LVG
open drain gate
(internal)
comp Vref
CP+
PROTECTION
Fast shut down
:
the driver outputs are set in SD state immediately after the comparator
triggering even if the SD signal has not yet reach the lower input threshold
disable time
SD/OD
AM12947v1

STGIPN3H60-E

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IGBT Modules
Lifecycle:
New from this manufacturer.
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