Functional Description
MC13192/MC13193 Technical Data, Rev. 3.1
Freescale Semiconductor 11
6 Functional Description
6.1 MC13192/MC13193 Operational Modes
The MC13192/MC13193 has a number of operational modes that allow for low-current operation.
Transition from the Off to Idle mode occurs when RST
is negated. Once in Idle, the SPI is active and is
used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are
summarized, along with the transition times, in Table 7. Current drain in the various modes is listed in
Table 3, DC Electrical Characteristics.
6.2 Serial Peripheral Interface (SPI)
The host microcontroller directs the MC13192/MC13193, checks its status, and reads/writes data to the
device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction
between the host and the MC13192/MC13193 occurs as multiple 8-bit bursts on the SPI. The SPI signals
are:
1. Chip Enable (CE
) - A transaction on the SPI port is framed by the active low CE input signal. A
transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.
2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13192/MC13193. Data is
clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data
out changes state on the trailing (falling) edge of SPICLK.
NOTE
For Freescale microcontrollers, the SPI clock format is the clock phase
control bit CPHA = 0 and the clock polarity control bit CPOL = 0.
3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
4. Master In/Slave Out (MISO) - The MC13192/MC13193 presents data to the master on the MISO
output.
Table 7. MC13192/MC13193 Mode Definitions and Transition Times
Mode Definition
Transition Time
To or From Idle
Off All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated including
IRQ
10 - 25 ms to Idle
Hibernate Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is
retained.
7 - 20 ms to Idle
Doze Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 = 1
for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN
and can be
programmed to enter Idle Mode through an internal timer comparator.
(300 + 1/CLKO) µs
to Idle
Idle Crystal Reference Oscillator On with CLKO output available. SPI active.
Receive Crystal Reference Oscillator On. Receiver On. 144 µs from Idle
Transmit Crystal Reference Oscillator On. Transmitter On. 144 µs from Idle
