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MC13193FCR2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
Functional Description
MC13192/MC13193 Technical Data, Rev. 3.1
Freescale Semiconductor 13
6.2.2 SPI Transaction Operation
Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13192/MC13193 requires that
a complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The
assertion of CE
to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to
the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and
identifies the access as being a read or write operation. In this context, a write is data written to the
MC13192/MC13193 and a read is data written to the SPI master. The following SPI bursts will be either
the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).
Although the SPI bus is capable of sending data simultaneously between master and slave, the
MC13192/MC13193 never uses this mode. The number of data bytes (payload) will be a minimum of 2
bytes and can extend to a larger number depending on the type of access. After the final SPI burst, CE
is
negated to high to signal the end of the transaction. Refer to the MC13192/MC13193 Reference Manual,
(MC13192RM) for more details on SPI registers and transaction types.
An example SPI read transaction with a 2-byte payload is shown in Figure 9.
Figure 9. SPI Read Transaction Diagram
CE
SPICLK
MISO
MOSI
Valid
Valid Valid
Clock Burst
Header Read data
Pin Connections
MC13192/MC13193 Technical Data, Rev. 3.1
14 Freescale Semiconductor
7 Pin Connections
Table 8. Pin Function Description
Pin # Pin Name Type Description Functionality
1 RFIN- RF Input LNA negative differential input.
2 RFIN+ RF Input LNA positive differential input.
3 Not Used Tie to Ground.
4 Not Used Tie to Ground.
5 PAO+ RF Output /DC Input Power Amplifier Positive Output. Open drain. Connect
to V
DDA
.
6 PAO- RF Output/DC Input Power Amplifier Negative Output. Open drain.
Connect to V
DDA
.
7 SM Test mode pin. Tie to Ground Tie to Ground for
normal operation
8 GPIO4
1
Digital Input/ Output General Purpose Input/Output 4. See Footnote 1
9 GPIO3
1
Digital Input/ Output General Purpose Input/Output 3. See Footnote 1
10 GPIO2
1
Digital Input/ Output General Purpose Input/Output 2. When gpio_alt_en,
Register 9, Bit 7 = 1, GPIO2 functions as a “CRC
Valid” indicator.
See Footnote 1
11 GPIO1
1
Digital Input/ Output General Purpose Input/Output 1. When gpio_alt_en,
Register 9, Bit 7 = 1, GPIO1 functions as an “Out of
Idle” indicator.
See Footnote 1
12 RST Digital Input Active Low Reset. While held low, the IC is in Off
Mode and all internal information is lost from RAM and
SPI registers. When high, IC goes to IDLE Mode, with
SPI in default state.
13 RXTXEN
2
Digital Input Active High. Low to high transition initiates RX or TX
sequence depending on SPI setting. Should be taken
high after SPI programming to start RX or TX
sequence and should be held high through the
sequence. After sequence is complete, return
RXTXEN to low. When held low, forces Idle Mode.
See Footnote 2
14 ATTN
2
Digital Input Active Low Attention. Transitions IC from either
Hibernate or Doze Modes to Idle.
See Footnote 2
15 CLKO Digital Output Clock output to host MCU. Programmable frequencies
of:
16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 62.5 kHz,
32.786+ kHz (default),
and 16.393+ kHz.
16 SPICLK
2
Digital Clock Input External clock input for the SPI interface. See Footnote 2
17 MOSI
2
Digital Input Master Out/Slave In. Dedicated SPI data input. See Footnote 2
18 MISO
3
Digital Output Master In/Slave Out. Dedicated SPI data output. See Footnote 3
19 CE
2
Digital Input Active Low Chip Enable. Enables SPI transfers. See Footnote 2
Pin Connections
MC13192/MC13193 Technical Data, Rev. 3.1
Freescale Semiconductor 15
20 IRQ Digital Output Active Low Interrupt Request. Open drain device.
Programmable 40
k
Ω internal pull-up.
Interrupt can be
serviced every 6 µs
with <20 pF load.
Optional external
pull-up must be >4
k
Ω.
21 VDDD Power Output Digital regulated supply bypass. Decouple to ground.
22 VDDINT Power Input Digital interface supply & digital regulator input.
Connect to Battery.
2.0 to 3.4 V.
Decouple to ground.
23 GPIO5
1
Digital Input/Output General Purpose Input/Output 5. See Footnote 1
24 GPIO6
1
Digital Input/Output General Purpose Input/Output 6. See Footnote 1
25 GPIO7
1
Digital Input/Output General Purpose Input/Output 7. See Footnote 1
26 XTAL1 Input Crystal Reference oscillator input. Connect to 16 MHz
crystal and load
capacitor.
27 XTAL2 Input/Output Crystal Reference oscillator output
Note: Do not load this pin by using it as a 16 MHz
source. Measure 16 MHz output at Pin 15,
CLKO, programmed for 16 MHz. See the
MC13192/MC13193 Reference Manual for details.
Connect to 16 MHz
crystal and load
capacitor.
28 VDDLO2 Power Input LO2 VDD supply. Connect to VDDA externally.
29 VDDLO1 Power Input LO1 VDD supply. Connect to VDDA externally.
30 VDDVCO Power Output VCO regulated supply bypass. Decouple to ground.
31 VBATT Power Input Analog voltage regulators Input. Connect to Battery. Decouple to ground.
32 VDDA Power Output Analog regulated supply Output. Connect to directly
VDDLO1 and VDDLO2 externally and to PAO±
through a frequency trap.
Note: Do not use this pin to supply circuitry external to
the chip.
Decouple to ground.
EP Ground External paddle / flag ground. Connect to ground.
1
The transceiver GPIO pins default to inputs at reset. There are no programmable pullups on these pins. Unused GPIO pins
should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state.
2
During low power modes, input must remain driven by MCU.
3
By default MISO is tri-stated when CE is negated. For low power operation, miso_hiz_en (Bit 11, Register 07) should be set
to zero so that MISO is driven low when CE
is negated.
Table 8. Pin Function Description (continued)
Pin # Pin Name Type Description Functionality
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

MC13193FCR2

Mfr. #:
Buy MC13193FCR2
Manufacturer:
NXP / Freescale
Description:
RF Transceiver ABEL ZIGBEE TRANS
Lifecycle:
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