Block Diagrams
MC13192/MC13193 Technical Data, Rev. 3.1
4 Freescale Semiconductor
3 Block Diagrams
Figure 1 shows a simplified block diagram of the MC13192/MC13193 which is an 802.15.4 Standard
compatible transceiver that provides the functions required in the physical layer (PHY) specification.
Figure 1. MC13192 Simplified Block Diagram
Figure 2 shows the basic system block diagram for the MC13192/MC13193 in an application. Interface
with the transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access
control (MAC), drivers, and network and application software (as required) reside on the host processor.
The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on
application requirements.
Figure 2. System Level Block Diagram
Phase Shift Modulator
RST
GPIO1
GPIO2
GPIO3
GPIO4
XTAL2
XTAL1
RFIN-
RFIN+
PAO+
PAO-
MOSI
MISO
SPICLK
RXTXEN
CE
ATTN
GPIO5
GPIO6
GPIO7
Receive
Packet RAM
Transmit
Packet RAM 1
Transmit RAM
Arbiter
Receive RAM
Arbiter
PA
VCO
Crystal
Oscillator
Sy mbol
Generation
FCS
Generation
Header
Generation
MUX
Sequence
Manager
(Control Logic)
VDDLO2
÷ 4
256 MHz
2.45 GHz
LNA
1st IF Mixer
IF = 65 M Hz
2nd IF Mix er
IF = 1 M Hz
PMA
Decimation
Filter
Matched
Filter
Baseband
Mixer
DCD
Correlator
Symbol
Synch & Det
CCA
Packet
Processor
IR Q
Arbiter
24 Bit Event Timer
IR Q
16 MHz
AGC
Analog
Regulator VBATT
Digital
Regulator L
Digital
Regulator H
Pow er-Up
Control
Logic
Crystal
Regulator
VCO
Regulator
VDDINT
Programmable
Prescaler
CLKO
4 Programmable
Timer Comparators
Synthesizer
VDDD
VDDVCO
SERIAL
PERIPHERAL
INTERFACE
(SPI)
VDDA
VDDLO1
Transmit
Packet RAM 2
Analog Receiver
MC13192/MC13193
Frequency
Generation
Analog
Transmitter
Voltage
Regulators
Power Up
Management
Control
Logic
Buffer RAM
Digital Transceiver
SPI
and GPIO
Microcontroller
SPI
ROM
(Flash)
RAM
CPU A/D
Timer
Application
IRQ Arbiter
RAM Arbiter
Timer
Network
MAC
PHY Driver
Data Transfer Modes
MC13192/MC13193 Technical Data, Rev. 3.1
Freescale Semiconductor 5
4 Data Transfer Modes
The MC13192/MC13193 has two data transfer modes:
1. Packet Mode — Data is buffered in on-chip RAM
2. Streaming Mode — Data is processed word-by-word
The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary
applications, packet mode can be used to conserve MCU resources.
4.1 Packet Structure
Figure 3 shows the packet structure of the MC13192/MC13193. Payloads of up to 125 bytes are supported.
The MC13192/MC13193 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a
one-byte Frame Length Indicator (FLI) before the data. A two-byte Frame Check Sequence (FCS) is
calculated and appended to the end of the data.
Figure 3. MC13192/MC13193 Packet Structure
4.2 Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
the baseband energy integrated over a specific time interval. The digital back end performs Differential
Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset
QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.
The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in
RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the
transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured
over a 64 µs period after the packet preamble and stored in RAM.
If the MC13192/MC13193 is in packet mode, the data is processed as an entire packet. The MCU is
notified that an entire packet has been received via an interrupt.
If the MC13192/MC13193 is in streaming mode, the MCU is notified by an interrupt on a word-by-word
basis.
Figure 4 shows CCA reported power level versus input power. Note that CCA reported power saturates at
about -57 dBm input power which is well above 802.15.4 Standard requirements.
Preamble SFD FLI Payload Data FCS
4 bytes 1 byte 1 byte 125 bytes maximum 2 bytes
Data Transfer Modes
MC13192/MC13193 Technical Data, Rev. 3.1
6 Freescale Semiconductor
Figure 4. Reported Power Level versus Input Power in Clear Channel Assessment Mode
Figure 5 shows energy detection/LQI reported level versus input power.
NOTE
For both graphs the required 802.15.4 Standard accuracy and range limits
are shown.
Figure 5. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator
-100
-90
-80
-70
-60
-50
-90 -80 -70 -60 -50
Input Pow er (dBm)
Reported Power Level (dBm)
802.15.4 Accuracy
and range Requirements
-85
-75
-65
-55
-45
-35
-25
-15
-85 -75 -65 -55 -45 -35 -25 -15
Input Power Level (dBm)
Reported Power Level (dBm)
802.15.4 Accuracy
and Range Requirements

MC13193FCR2

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
RF Transceiver ABEL ZIGBEE TRANS
Lifecycle:
New from this manufacturer.
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