ADF4110BRU-REEL Datasheet ADF4111BRUZ-RL7, ADF4110BRUZ, ADF4113BRUZ-REEL7 | P19-P21

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113

Rev. F | Page 19 of 28

FUNCTION LATCH

The on-chip function latch is programmed with C2, C1 set to 1.

Table 9 shows the input data format for programming the

function latch.

Counter Reset

DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter

and the AB counters are reset. For normal operation, this bit

should be 0. Upon powering up, the F1 bit must be disabled,

and the N counter resumes counting in “close” alignment with

the R counter. (The maximum error is one prescaler cycle.)

Power-Down

DB3 (PD1) and DB21 (PD2) on the ADF411x provide

program-mable power-down modes. They are enabled by the

CE pin.

When the CE pin is low, the device is immediately disabled

regardless of the states of PD2, PD1.

In the programmed asynchronous power-down, the device

powers down immediately after latching a 1 into Bit PD1,

provided PD2 has been loaded with a 0.

In the programmed synchronous power-down, the device

power-down is gated by the charge pump to prevent unwanted

frequency jumps. Once power-down is enabled by writing a 1

into Bit PD1 (provided a 1 has also been loaded to PD2), the

device goes into power-down on the next charge pump event.

When a power-down is activated (either synchronous or

asynchronous mode including CE pin activated power-down),

the following events occur:

• All active dc current paths are removed.

• The R, N, and timeout counters are forced to their load

state conditions.

• The charge pump is forced into three-state mode.

• The digital clock detect circuitry is reset.

• The RFIN input is debiased.

• The reference input buffer circuitry is disabled.

• The input register remains active and capable of loading

and latching data.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1 on

the ADF4110 family. Table 9 shows the truth table.

Fastlock Enable Bit

DB9 of the function latch is the fastlock enable bit. Fastlock is

enables only when this is 1.

Fastlock Mode Bit

DB10 of the function latch is the fastlock enable bit. When

fastlock is enabled, this bit determines which fastlock mode is

used. If the fastlock mode bit is 0, fastlock mode 1 is selected; if

the fastlock mode bit is 1, fastlock mode 2 is selected.

Fastlock Mode 1

The charge pump current is switched to the contents of Current

Setting 2.

The device enters fastlock by having a 1 written to the CP gain

bit in the AB counter latch. The device exits fastlock by having a

0 written to the CP gain bit in the AB counter latch.

Fastlock Mode 2

The charge pump current is switched to the contents of Current

Setting 2. The device enters fastlock by having a 1 written to the

CP gain bit in the AB counter latch. The device exits fastlock

under the control of the timer counter. After the timeout period

determined by the value in TC4 through TC1, the CP gain bit in

the AB counter latch is automatically reset to 0 and the device

reverts to normal mode instead of fastlock. See Table 9 for the

timeout periods.

Timer Counter Control

The user has the option of programming two charge pump cur-

rents. Current Setting 1 is meant to be used when the RF output

is stable and the system is in a static state. Current Setting 2 is

meant to be used when the system is dynamic and in a state of

change (i.e., when a new output frequency is programmed).

The normal sequence of events is as follows:

The user initially decides what the preferred charge pump

currents are going to be. For example, they may choose 2.5 mA

as Current Setting 1 and 5 mA as Current Setting 2.

At the same time, they must also decide how long they want the

secondary current to stay active before reverting to the primary

current. This is controlled by the timer counter control bits,

DB14 through DB11 (TC4 through TC1) in the function latch.

The truth table is given in Table 10.

A user can program a new output frequency simply by pro-

gramming the AB counter latch with new values for A and B. At

the same time, the CP gain bit can be set to 1, which sets the

charge pump with the value in CPI6–CPI4 for a period deter-

mined by TC4 through TC1. When this time is up, the charge

pump current reverts to the value set by CPI3–CPI1. At the

same time, the CP gain bit in the AB counter latch is reset to 0

and is ready for the next time the user wishes to change the

frequency.

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet

Rev. F | Page 20 of 28

Note that there is an enable feature on the timer counter. It is

enabled when Fastlock Mode 2 is chosen by setting the fastlock

mode bit (DB10) in the function latch to 1.

Charge Pump Currents

CPI3, CPI2, and CPI1 program Current Setting 1 for the charge

pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the

charge pump. The truth table is given in Table 10.

Prescaler Value

P2 and P1 in the function latch set the prescaler values. The

prescaler value should be chosen so that the prescaler output

frequency is always less than or equal to 200 MHz. Thus, with

an RF frequency of 2 GHz, a prescaler value of 16/17 is valid but

a value of 8/9 is not.

PD Polarity

This bit sets the phase detector polarity bit. See Table 10.

CP Three-State

This bit controls the CP output pin. With the bit set high, the

CP output is put into three-state. With the bit set low, the CP

output is enabled.

INITIALIZATION LATCH

When C2, C1 = 1, 1, the initialization latch is programmed.

This is essentially the same as the function latch (programmed

when C2, C1 = 1, 0).

However, when the initialization latch is programmed, an addi-

tional internal reset pulse is applied to the R and AB counters.

This pulse ensures that the AB counter is at load point when the

AB counter data is latched, and the device begins counting in

close phase alignment.

If the latch is programmed for synchronous power-down (CE

pin high; PD1 bit high; PD2 bit low), the internal pulse also

triggers this power-down. The prescaler reference and the

oscillator input buffer are unaffected by the internal reset pulse,

so close phase alignment is maintained when counting resumes.

When the first AB counter data is latched after initialization, the

internal reset pulse is again activated. However, successive AB

counter loads after this will not trigger the internal reset pulse.

DEVICE PROGRAMMING AFTER INITIAL

POWER-UP

After initial power-up of the device, there are three ways to

program the device.

Initialization Latch Method

Apply V

. Program the initialization latch (11 in 2 LSBs of

input word). Make sure the F1 bit is programmed to 0. Then, do

an R load (00 in 2 LSBs). Then do an AB load (01 in 2 LSBs).

When the initialization latch is loaded, the following occurs:

1. The function latch contents are loaded.

2. An internal pulse resets the R, A, B, and timeout counters

to load state conditions and three-states the charge pump.

Note that the prescaler band gap reference and the oscil-

lator input buffer are unaffected by the internal reset pulse,

allowing close phase alignment when counting resumes.

3. Latching the first AB counter data after the initialization

word activates the same internal reset pulse. Successive AB

loads do not trigger the internal reset pulse unless there is

another initialization.

CE Pin Method

1. Apply V

2. Bring CE low to put the device into power-down. This is an

asynchronous power-down in that it happens immediately.

3. Program the function latch (10). Program the R counter

latch (00). Program the AB counter latch (01).

4. Bring CE high to take the device out of power-down. The R

and AB counters now resume counting in close alignment.

After CE goes high, a duration of 1 µs may be required for the

prescaler band gap voltage and oscillator input buffer bias to

reach steady state.

CE can be used to power the device up and down in order to

check for channel activity. The input register does not need to

be reprogrammed each time the device is disabled and enabled

as long as it has been programmed at least once after V

was

initially applied.

Counter Reset Method

1. Apply V

2. Do a function latch load (10 in 2 LSBs). As part of this,

load 1 to the F1 bit. This enables the counter reset.

3. Do an R counter load (00 in 2 LSBs). Do an AB counter

load (01 in 2 LSBs). Do a function latch load (10 in 2

LSBs). As part of this, load 0 to the F1 bit. This disables the

counter reset.

This sequence provides the same close alignment as the initiali-

zation method. It offers direct control over the internal reset.

Note that counter reset holds the counters at load point and

three states the charge pump but does not trigger synchronous

power-down. The counter reset method requires an extra

function latch load compared to the initialization latch method.

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113

Rev. F | Page 21 of 28

RESYNCHRONIZING THE PRESCALER OUTPUT

Table 7 (the Reference Counter Latch Map) shows two bits,

DB22 and DB21, which are labeled DLY and SYNC,

respectively. These bits affect the operation of the prescaler.

With SYNC = 1, the prescaler output is resynchronized with the

RF input. This has the effect of reducing jitter due to the

prescaler and can lead to an overall improvement in synthesizer

phase noise performance. Typically, a 1 dB to 2 dB

improvement is seen in the ADF4113. The lower bandwidth

devices can show an even greater improvement. For example,

the ADF4110 phase noise is typically improved by 3 dB when

SYNC is enabled.

With DLY = 1, the prescaler output is resynchronized with a

delayed version of the RF input.

If the SYNC feature is used on the synthesizer, some care must

be taken. At some point, (at certain temperatures and output

frequencies), the delay through the prescaler coincides with the

active edge on RF input; this causes the SYNC feature to break

down. It is important to be aware of this when using the SYNC

feature. Adding a delay to the RF signal, by programming

DLY = 1, extends the operating frequency and temperature

somewhat. Using the SYNC feature also increases the value of

the AI

for the device. With a 900 MHz output, the ADF4113

increases by about 1.3 mA when SYNC is enabled and by

an additional 0.3 mA if DLY is enabled.

All the typical performance plots in this data sheet, except for

Figure 8, apply for DLY and SYNC = 0, i.e., no resynchroniza-

tion or delay enabled.

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