ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet
Rev. F | Page 22 of 28
APPLICATIONS
LOCAL OSCILLATOR FOR GSM BASE STATION TRANSMITTER
Figure 33 shows the ADF4111/ADF4112/ADF4113 being used
with a VCO to produce the LO for a GSM base station
transmitter.
The reference input signal is applied to the circuit at FREF
IN
and, in this case, is terminated in 50 Ω. A typical GSM system
would have a 13 MHz TCXO driving the reference input with-
out any 50 Ω termination. In order to have channel spacing of
200 kHz (GSM standard), the reference input must be divided
by 65, using the on-chip reference divider of the ADF4111/
ADF4112/ADF4113.
The charge pump output of the ADF4111/ADF4112/ADF4113
(Pin 2) drives the loop filter. In calculating the loop filter
component values, a number of items need to be considered. In
this example, the loop filter was designed so that the overall
phase margin for the system would be 45 degrees. Other PLL
system specifications are
K
D
= 5 mA
K
V
= 12 MHz/V
Loop Bandwidth = 20 kHz
F
REF
= 200 kHz
N = 4500
Extra Reference Spur Attenuation = 10 dB
All of these specifications are needed and used to come up with
the loop filter component values shown in Figure 33.
The loop filter output drives the VCO, which in turn is fed back
to the RF input of the PLL synthesizer. It also drives the RF out-
put terminal. A T-circuit configuration provides 50 matching
between the VCO output, the RF output, and the RF
IN
terminal
of the synthesizer.
In a PLL system, it is important to know when the system is in
lock. In Figure 33, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be pro-
grammed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.
ADF4111
ADF4112
ADF4113
CE
CLK
DATA
LE
1000pF
1000pF
REF
IN
100pF
CP
MUXOUT
CPGND
AGND
DGND
1nF
8.2nF
620pF
100pF
51
1
3.3k
5.6k
100pF
18
1
TO BE USED WHEN GENERATOR SOURCE IMPEDANCE IS 50.
2
OPTIONAL MATCHING RESISTOR DEPENDING ON RF
OUT
FREQUENCY.
DECOUPLING CAPACITORS ON AV
DD
, DV
DD
, AND V
P
OF THE ADF411x
AND ON THE POSITIVE SUPPLY OF THE VCO190-902T HAVE BEEN
OMITTED FROM THE DIAGRAM TO INCREASE CLARITY.
SPI COMPATIBLE SERIAL BUS
R
SET
RF
IN
A
RF
IN
B
AV
DD
DV
DD
V
P
FREF
IN
V
DD
V
P
LOCK
DETECT
V
CC
VCO190-902T
18
18
100pF
RF
OUT
4.7k
7
15
16
8
2
14
6
5
1
9
4
3
B
C
P
51
2
03496-0-038
Figure 33. Local Oscillator for GSM Base Station
Data Sheet ADF4110/ADF4111/ADF4112/ADF4113
Rev. F | Page 23 of 28
ADF4111
ADF4112
ADF4113
2.7k
VCO
GND
18
100pF
100pF
18
18
RF
OUT
FREF
IN
51
100pF
100pF
RF
IN
A
RF
IN
B
POWER SUPPLY CONNECTIONS AND DECOUPLING
CAPACITORS ARE OMITTED FOR CLARITY.
R
SET
REF
IN
CP
LOOP
FILTER
CE
CLK
DATA
LE
SPI COMPATIBLE SERIAL BUS
AD5320
12-BIT
V-OUT DAC
MUXOUT
LOCK
DETECT
INPUT
OUTPUT
2
14
6
5
1
8
03496-0-039
Figure 34. Driving the R
SET
Pin with a D/A Converter
USING A D/A CONVERTER TO DRIVE THE R
SET
PIN
A D/A converter can be used to drive the R
SET
pin of the
ADF4110 family, thus increasing the level of control over the
charge pump current, I
CP
. This can be advantageous in wide-
band applications where the sensitivity of the VCO varies over
the tuning range. To compensate for this, the I
CP
may be varied
to maintain good phase margin and ensure loop stability. See
Figure 34.
SHUTDOWN CIRCUIT
The attached circuit in Figure 35 shows how to shut down both
the ADF4110 family and the accompanying VCO. The ADG701
switch goes closed circuit when a Logic 1 is applied to the IN
input. The low cost switch is available in both SOT-23 and
MSOP packages.
WIDEBAND PLL
Many of the wireless applications for synthesizers and VCOs in
PLLs are narrow band in nature. These applications include the
various wireless standards like GSM, DSC1800, CDMA, and
WCDMA. In each of these cases, the total tuning range for the
local oscillator is less than 100 MHz. However, there are also
wideband applications for which the local oscillator could have
a tuning range as wide as an octave. For example, cable TV
tuners have a total range of about 400 MHz. Figure 36 shows an
application where the ADF4113 is used to control and program
the Micronetics M3500-2235. The loop filter was designed for
an RF output of 2900 MHz, a loop bandwidth of 40 kHz, a PFD
frequency of 1 MHz, I
CP
of 10 mA (2.5 mA synthesizer I
CP
multiplied by the gain factor of 4), VCO K
D
of 90 MHz/V
(sensitivity of the M3500-2235 at an output of 2900 MHz), and
a phase margin of 45°C.
In narrow-band applications, there is generally a small variation
in output frequency (generally less than 10%) and a small
variation in VCO sensitivity over the range (typically 10% to
15%). However, in wideband applications, both of these
parameters have a much greater variation. In Figure 36, for
example, there is a 25% and +17% variation in the RF output
from the nominal 2.9 GHz. The sensitivity of the VCO can vary
from 120 MHz/V at 2750 MHz to 75 MHz/V at 3400 MHz
(+33%, 17%). Variations in these parameters change the loop
bandwidth. This in turn can affect stability and lock time. By
changing the programmable I
CP
, it is possible to get compensa-
tion for these varying loop conditions and ensure that the loop
is always operating close to optimal conditions.
ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet
Rev. F | Page 24 of 28
V
DD
V
P
AV
DD
DV
DD
ADF4110
ADF4111
ADF4112
ADF4113
V
P
4.7k
VCO
V
CC
GND
18
18
18
100pF
100pF
RF
OUT
REF
IN
51
100pF
100pF
DNGP
C
DNG
A
DN
GD
RF
IN
A
RF
IN
B
DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE
BEEN OMITTED FROM THE DIAGRAM TO INCREASE CLARITY.
R
SET
CP
CE
POWER-DOWN CONTROL
V
DD
S
IN
D
GND
LOOP
FILTER
ADG701
FREF
IN
1
8
7
15
16
2
6
5
9
43
10
03496-0-040
Figure 35. Local Oscillator Shutdown Circuit
V
DD
V
P
AV
DD
DV
DD
ADF4113
V
P
2.8nF
680
130pF
3.3k
19nF
M3500-2235
V
CC
18
18
18
100pF
100pF
RF
OUT
1000pF
1000pF
51
REF
IN
MUXOUT
LOCK
DETECT
51
100pF
100pF
DNGPC
DNGA
DNGD
RF
IN
A
RF
IN
B
CE
CLK
DATA
LE
SUBLAIRESELBITAPMOC-IPS
DECOUPLING CAPACITORS ON AV
DD
, DV
DD
, V
P
OF THE ADF4113
AND ON VCC OF THE M3500-2250 HAVE BEEN OMITTED FROM
THE DIAGRAM TO AID CLARITY.
R
SET
CP
4.7k
12V
V_TUNE
GND
20V
1k
AD820
3k
OUT
FREF
IN
3 4 9
5
6
14
2
1
8
7 15 16
03496-0-041
Figure 36. Wideband Phase-Locked Loop

ADF4110BRU-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL SGL Integer-N 550 MHz
Lifecycle:
New from this manufacturer.
Delivery:
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