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SII163BCTG100

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
SiI 163B PanelLink Receiver
Data Sheet
9 SiI-DS-0055-C
DE
SCDT
DE
SCDT
T
TFSC
T
THSC
Figure 9. SCDT Timing from DE Inactive or Active
ODCK
DE
QE[23:0]]
QO[23:0]
FIRST DATA THIRD DATA
Internal
ODCK * 2
SECOND
FOURTH DATA
T
ST
Figure 10. Two Pixel per Clock Staggered Output Timing Diagram
SiI 163B PanelLink Receiver
Data Sheet
10 SiI-DS-0055-C
Pin Descriptions
Output Pins
Pin
Name
Pin # Type Description
QE23-
QE0
See
SiI 163B
Pin
Diagram
Out Output Even Data[23:0]. Refer to the Dual Link section on page 13 for details.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section on page 20, which tabulates the
relationship between the input data to the transmitter and output data from the
receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-
state) mode. A weak internal pull-down device brings each output to ground.
QO23-
QO0
See
SiI 163B
Pin
Diagram
Out Output Odd Data[23:0]. Refer to the Dual Link section on page 13 for details.
Output data is synchronized with output data clock (ODCK).
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section on page 20, which tabulates the
relationship between the input data to the transmitter and output data from the
receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-
state) mode. A weak internal pull-down device brings each output to ground.
ODCK 44 Out Output Data Clock. This output can be inverted using the OCK_INV# pin. A low level
on PD# or PDO# will put the output driver into a high impedance (tri-state) mode. A
weak internal pull-down device brings the output to ground.
DE 46 Out Output Data Enable. This signal qualifies the active data area. A HIGH level signifies
active display time and a LOW level signifies blanking time. This output signal is
synchronized with the output data. A low level on PD# or PDO# will put the output
driver into a high impedance (tri-state) mode. A weak internal pull-down device
brings the output to ground.
HSYNC
VSYNC
CTL1
CTL2
CTL3
48
47
40
41
42
Out
Out
Out
Out
Out
Horizontal Sync input control signal.
Vertical Sync input control signal.
General output control signal 1. This output is not powered down by PDO#.
General output control signal 2.
General output control signal 3.
A low level on PD# or PDO# will put the output drivers (except CTL1 by PDO#) into
a high impedance (tri-state) mode. A weak internal pull-down device brings each
output to ground.
SiI 163B PanelLink Receiver
Data Sheet
11 SiI-DS-0055-C
Configuration Pins
Pin Name Pin # Type Description
OCK_INV# 100 In ODCK Polarity. A LOW level selects normal ODCK output. A HIGH level selects
inverted ODCK output. All other output signals are unaffected by this pin. They will
maintain the same timing no matter the setting of OCK_INV# pin
PIXS/M_S 4 In When S_D pin is LOW (Single Link), this pin selects 1-pixel/clock mode (LOW) or 2-
pixel/clock mode (HIGH). When S_D pin is HIGH (Dual Link), this pin is Master
Slave Mode Select.
STAG_OUT#
/SYNC
7 In When S_D pin is LOW (Single Link), this pin selects Staggered Output. A HIGH level
selects normal simultaneous outputs on all odd and even data lines. A LOW level
selects staggered output drive. This function is only available in 2-pixels per clock
mode. When S_D pin is HIGH (Dual Link), this pin is an input pin on the Slave
receiver for the DE signal from the master receiver, used for synchronization.
ST 3 In Output Drive. A HIGH level selects HIGH output drive strength. A LOW level selects
LOW output drive strength.
S_D 1 In Single/Dual Link Mode. A LOW level selects Single Link mode. A HIGH level
selects Dual Link mode. This affects the operation of SYNC, M_S and the two 24-bit
data output buses.
Power Management Pins
Pin
Name
Pin # Type Description
SCDT 8 Out Sync Detect. A HIGH level is outputted when DE is actively toggling indicating that the
link is alive. A LOW level is outputted when DE is inactive, indicating the link is down.
Can be connected to PDO# to power down the outputs when DE is not detected. The
SCDT output itself, however, remains in the active mode at all times.
PDO# 9 In Output Driver Power Down (active LOW). A HIGH level indicates normal operation. A
LOW level puts all the output drivers only (except SCDT and CTL1) into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to
ground. PDO# is a sub-set of the PD# description. The chip is not in power-down mode
with this pin. SCDT and CTL1 are not tri-stated by this pin.
PD# 2 In Power Down (active LOW). A HIGH level indicates normal operation. A LOW level
indicates power down mode. During power down mode, all the output drivers are put
into a high impedance (tri-state) mode. A weak internal pull-down device brings each
output to ground. Additionally, all analog logic is powered down, and all inputs are
disabled.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

SII163BCTG100

Mfr. #:
Buy SII163BCTG100
Manufacturer:
Lattice
Description:
25-165MHZ DUAL, PANELLINK RX G-P
Lifecycle:
New from this manufacturer.
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