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SII163BCTG100

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
SiI 163B PanelLink Receiver
Data Sheet
18 SiI-DS-0055-C
Figure 13 is an example of the output timing diagram of the Slave receiver. When the Slave receiver’s SCDT
signal is LOW, the Slave receiver is inactive and has tri-stated all its outputs. This is because the system is
sending data with a pixel clock of less than or equal to 165 MHz on the link connected to the Master receiver only.
There are no signals being sent to the Slave receiver from the system.
When the Slave receiver’s SCDT signal goes HIGH, the system is sending data with a pixel clock greater than
165 MHz and less than 330 MHz. The system is sending the EVEN pixel to the Master receiver and the ODD
pixel to the Slave receiver. The Slave receiver is receiving signals from the system and has asserted its SCDT
signal to the Master receiver. This puts the Master receiver in Dual Link 1-pixel/clock mode. The Slave receiver is
outputting the ODD pixel data on its EVEN pixel bus. The Master receiver outputs the EVEN pixels. The Master
receiver has tri-stated its ODD pixel bus to allow the Slave receiver to send ODD pixel data.
DE[23:0] DE[23:0] DE[23:0] DE[23:0]
Slave SCDT
(Master S_D)
Master ODCK
Slave DO[23:0]
Slave DE[23:0]
Slave is receiving Data from the System and
outputs it on DE[23:0]. DO[23:0] is kept Tri-Stated.
Slave is not receiving
Data from the System
and Tri-States its Data
bus and Clock.
1-pixel/clock
Figure 13. Timing Diagram of Slave's Output
Figure 14 is an example of the data that is driven out by the two receivers. All the control signals, including
ODCK, are sent by the Master receiver.
DE[23:0] DE[23:0]
DO[23:0] DO[23:0]
DE[23:0] DE[23:0]
DO[23:0] DO[23:0]
DE[23:0] DE[23:0]
DO[23:0] DO[23:0]
Slave SCDT
(Master S_D)
Master ODCK
(2-pixel/clock
Mode)
Panel DO[23:0]
Panel DE[23:0]
Slave is not Active.
Outputs are Tri-Stated
Master is in Single Link
Two-Pixels/Clock Mode.
Master is outputting
both Even and Odd
pixels.
Master is in Dual Link One-Pixel/Clock Mode.
Master is outputting Even pixels. Master has Tri-
Stated its Odd pixel bus to allow Slave to output
Odd pixel data.
Slave is in Dual Link One-Pixel/Clock Mode.
Slave is outputing Odd pixels.
System is sending Data
only to the Master. Only
clock is sent to the
Slave.
System is sending the Even pixel data to the
Master and the Odd pixel data to the Slave.
Figure 14. Single/Dual Link Timing Diagram
SiI 163B PanelLink Receiver
Data Sheet
19 SiI-DS-0055-C
Table 4. DVI-D Connector to SiI 163B for Dual Link Application Pin Connection
DVI-D Connector
SiI 163B - Master SiI 163B - Slave
Pin # Signal Pin # Pin Name Pin # Pin Name
1 TMDS Data2- 81 Rx2- for Master
2 TMDS Data2+ 80 Rx2+ for Master
3 TMDS Data2/4 Shield
4 TMDS Data4- 86 Rx1- for Slave
5 TMDS Data4+ 85 Rx1+ for Slave
6 DDC Clock
7 DDC Data
8 NC
9 TMDS Data1- 86 Rx1- for Master
10 TMDS Data1+ 85 Rx1+ for Master
11 TMDS Data1/3 Shield
12 TMDS Data3- 91 Rx0- for Slave
13 TMDS Data3+ 90 Rx0+ for Slave
14 +5V Power
15 Ground
16 Hot Plug Detect
17 TMDS Data0- 91 Rx0- for Master
18 TMDS Data0+ 90 Rx0+ for Master
19 TMDS Data0/5 Shield
20 TMDS Data5- 81 Rx2- for Slave
21 TMDS Data5+ 80 Rx2+ for Slave
22 TMDS Clock Shield
23 TMDS Clock+ 93 RxC+ for Master 93 RxC+ for Slave
24 TMDS Clock- 94 RxC- for Master 94 RxC- for Slave
Clock Detect Function
The SiI 163B includes a new power saving feature: power down with clock detect circuit. The SiI 163B will go into
a low power mode when there is no video clock coming from the transmitter. In this mode, the entire chip is
powered down except the clock detect circuitry. During this mode, digital I/O are set to a high impedance (tri-
state) mode. A weak internal pull-down device brings each output to ground. The device power down and wake-
up times are shown in Figure 6 and Figure 7.
OCK_INV# Function
OCK_INV# affects only the phase of the clock output as
indicated in Figure 15. OCK_INV# does not change the
timing for the internal data latching. This timing is
shown in Figure 5.
QE[23:0]
QO[23:0]
ODCK
OCK_INV#
Figure 15. Block Diagram for OCK_INV#
SiI 163B PanelLink Receiver
Data Sheet
20 SiI-DS-0055-C
TFT Panel Data Mapping
Table 5 summarizes the output data mapping in one pixel per clock mode for the SiI 163B. This output data
mapping is dependent upon the PanelLink transmitters having the exact same type of input data mappings.
Table 6 summarizes the output data mapping in two pixel per clock mode. More detailed mapping information is
found on the following pages. Refer to application note SiI-AN-0007 for DSTN applications.
Note that the choice of one pixel/clock versus two pixel/clock on the transmitter side has no effect on the choice of
one pixel/clock versus two pixel/clock on the receiver side. The data is always sent across the link at the pixel
clock rate. Therefore, designers using PanelLink receivers do not need to know how the transmitter has taken in
pixel data on the transmitter input pins.
Table 5. One Pixel/Clock Mode Data Mapping
SiI 163B
DATA
1-Pixel/Clock Output
18bpp 24bpp
BLUE[7:0] QE[7:2] QE[7:0]
GREEN[7:0] QE[15:10] QE[15:8]
RED[7:0] QE[23:18] QE[23:16]
Table 6. Two Pixel/Clock Mode Data Mapping
SiI 163B
DATA
2-Pixel/Clock Output
18bpp 24bpp
BLUE[7:0] – 0 QE[7:2] QE[7:0]
GREEN[7:0] – 0 QE[15:10] QE[15:8]
RED[7:0] – 0 QE[23:18] QE[23:16]
BLUE[7:0] – 1 QO[7:2] QO[7:0]
GREEN[7:0] – 1 QO[15:10] QO[15:8]
RED[7:0] – 1 QO[23:18] QO[23:16]
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

SII163BCTG100

Mfr. #:
Buy SII163BCTG100
Manufacturer:
Lattice
Description:
25-165MHZ DUAL, PANELLINK RX G-P
Lifecycle:
New from this manufacturer.
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