SiI 163B PanelLink Receiver
Data Sheet
5 SiI-DS-0055-C
AC Specifications
Under normal operating conditions unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
T
DPS
Intra-Pair (+ to -) Differential Input Skew
1
165MHz 245 ps
T
CCS
Channel to Channel Differential Input Skew
1
165MHz 4 ns
T
IJIT
Worst Case Differential Input Clock Jitter 65 MHz 465 ps
tolerance
2,3
112 MHz 270 ps
165 MHz 182 ps
D
LHT
C
L
= 10pF; ST = 1 2.6 ns
Low-to-High Transition Time: Data and Controls
(70°C, 87.5 MHz, 2-pixel/clock, PIXS=1)
C
L
= 5pF; ST = 0 2.7 ns
C
L
= 10pF; ST = 1 2.4 ns
Low-to-High Transition Time: Data and Controls
(70°C, 165 MHz, 1-pixel/clock, PIXS=0)
C
L
= 5pF; ST = 0 3.0 ns
C
L
= 10pF; ST = 1 1.3 ns
Low-to-High Transition Time: ODCK
(70°C, 87.5 MHz, 2-pixel/clock, PIXS=1)
C
L
= 5pF; ST = 0 1.7 ns
C
L
= 10pF; ST = 1 1.4 ns
Low-to-High Transition Time: ODCK
(70°C, 165 MHz, 1-pixel/clock, PIXS=0)
C
L
= 5pF; ST = 0 1.7 ns
D
HLT
C
L
= 10pF; ST = 1 2.8 ns
High-to-Low Transition Time: Data and Controls
(70°C, 87.5 MHz, 2-pixel/clock, PIXS=1)
C
L
= 5pF; ST = 0 3.4 ns
C
L
= 10pF; ST = 1 2.3 ns
High-to-Low Transition Time: Data and Controls
(70°C, 165 MHz, 1-pixel/clock, PIXS=0)
C
L
= 5pF; ST = 0 3.3 ns
C
L
= 10pF; ST = 1 1.1 ns
High-to-Low Transition Time: ODCK
(70°C, 87.5 MHz, 2-pixel/clock, PIXS=1)
C
L
= 5pF; ST = 0 1.5 ns
C
L
= 10pF; ST = 1 1.2 ns
High-to-Low Transition Time: ODCK
(70°C, 165 MHz, 1-pixel/clock, PIXS=0)
C
L
= 5pF; ST = 0 1.5 ns
T
SETUP
C
L
= 10pF; ST = 1 0.9
(1.4)
6
ns
Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup
Time to ODCK falling edge (OCK_INV# = 0) or to
ODCK rising edge (OCK_INV# = 1) at 165 MHz
C
L
= 5pF; ST = 0 0.7
(0.5)
6
ns
T
HOLD
C
L
= 10pF; ST = 1
2.7
(2.3)
6
ns
Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time
from ODCK falling edge (OCK_INV# = 0) or from
ODCK rising edge (OCK_INV# = 1) at 165 MHz
C
L
= 5pF; ST = 0 3.0
(2.6)
6
ns
R
CIP
ODCK Cycle Time
1
(1-pixel/clock) 6.06 40 ns
F
CIP
ODCK Frequency
1
(1-pixel/clock) 25 165 MHz
R
CIP
ODCK Cycle Time
1
(2-pixels/clock) 12.1 80 ns
F
CIP
ODCK Frequency
1
(2-pixels/clock) 12.5 82.5 MHz
R
CIH
C
L
= 10pF; ST = 1 1.7 ns
ODCK High Time
4
C
L
= 5pF; ST = 0 1.3 ns
R
CIL
C
L
= 10pF; ST = 1 2.0 ns
ODCK Low Time
4
165 MHz, 1 pixel/clock,
PIXS=0.
C
L
= 5pF; ST = 0 1.4 ns
T
PDL
Delay from PD# / PDO# Low to high impedance outputs
1
10 ns
T
HSC
Link disabled (DE inactive) to SCDT low
1
100 ms
Link disabled (Tx power down) to SCDT low
5
250 ms
T
FSC
Link enabled (DE active) to SCDT high
1
25 40 DE edges
T
CLKPD
Delay from RXC+ Inactive to high impedance outputs RXC+ = 25MHz 10
µs
T
CLKPU
Delay from RXC+ active to data active RXC+ = 25MHz 100
µs
T
ST
ODCK high to even data output
1
0.25 R
CIP
T
OSK
Output Skew from Slave to Master Data buses
7
165 MHz 300 300 ps
