SiI 163B PanelLink Receiver
Data Sheet
32 SiI-DS-0055-C
Stabilized TMDS Inputs
The SCDT output of the slave SiI 163B receiver indicates the presence (or absence) of display data on the TMDS
link. Both incoming TMDS clock and data will output a HIGH via SCDT indicating that the encoded DE signal and
Clock from the TMDS transmitter is being detected and the link is active. In Dual Link mode the input Clock
signal is shared between Master and Slave SiI 163B.
When functioning in Single Link (in a Dual Link application), input TMDS data for Slave SiI 163B is absent, SCDT
output of the Slave SiI 163B will go low. However, system noise or coupled noise (above 20mV) can trigger the
differential input circuits of the receiver falsely indicating that display data is being received. In this condition, the
SiI 163B can assert SCDT High, even though the input data is invalid.
The SCDT output can be stabilized by introducing an offset voltage at the differential inputs. This can be
achieved by adding pull down resistors to the appropriate inputs. A nominal value of 2K ohms provides sufficient
offset between the + and – data differential inputs. In the application circuit, any value between 1.8K ohms and
2.5K ohms can be used with minimal effect on the single ended impedance.
Slave SiI 163B
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
~2K
Three pull down resistors should be placed
on either the + or – differential data input
pins. Figure 24 illustrates each + differential
input data pin pulled down by a nominal 2K
ohm resistor. The pull down resistors can be
placed either close to the receiver or the DVI
connector based on layout efficiency. Ensure
that the trace leading to the resistor and
ground is as short as possible to reduce
capacitive loading. The TMDS Clock (RXC+
and RXC–) input pins do not require pull
down resistors since they have internal pull
down resistors.
Figure 24. Stabilizing SCDT
Staggered Outputs and Two Pixels per Clock
PanelLink receivers offer two features that can minimize the switching effects of the high-speed output data bus:
two pixels per clock mode and staggered outputs.
The receiver can output one or two pixels in each output clock cycle. By widening the bus to two pixels per clock
whenever possible, the clock speed is halved and the switching period of the data signals themselves is twice as
long as in one pixel per clock mode. Typically, SXGA-resolution and above LCD panels expect to be connected
with a 36-bit or 48-bit bus, two pixels per clock. Most XGA-resolution and below LCD panels use an 18- to 24-bit
one pixel per clock interface.
When in two pixel per clock mode, the STAG_OUT# pin on receivers provides an additional means of reducing
simultaneous switching activity. When enabled (STAG_OUT# = Low), only half of the output data pins switch
together. The other half are switched one quarter clock cycle later. Note that both pixel buses use the same
clock. Therefore, the staggered bus will have one quarter clock cycle less setup time to the clock, and one
quarter clock cycle more hold time. Board designers driving into another clocked chip should take this into
account in their timing analysis.
Silicon Image recommends the use of STAG_OUT# and the two pixel per clock mode whenever possible.
Note that these features are limited when the SiI 163B is connected in Dual Link configuration.
