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AT21CS01-SSHM11-T

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However, if the device is busy, the master must drive SI/O for a longer time of t
DSCHG
to ensure the device
is reset as discussed in Interrupting the Device during an Active Operation. The Reset time forces any
internal charge storage within the device to be consumed, causing the device to lose all remaining
standby power available internally.
Upon SI/O being released for a sufficient amount of time to allow the device time to power-up and
initialize, the master must then always request a Discovery Response Acknowledge from the
AT21CS01/11 prior to any commands being sent to the device. The master can then determine if an
AT21CS01/11 is present by sampling for the Discovery Response Acknowledge from the device.
3.1.1.2 Device Response Upon Reset or Power-Up
After the device has been powered up or after the master has reset the device by holding the SI/O line
low for t
RESET
or t
DSCHG
, the master must then release the line which will be pulled high by an external
pull-up resistor. The master must then wait an additional minimum time of t
RRT
before the master can
request a Discovery Response Acknowledge from the device.
The Discovery Response Acknowledge sequence begins by the master driving the SI/O line low which
will start the AT21CS01/11 internal timing circuits. The master must continue to drive the line low for t
DRR
.
During the t
DRR
time, the AT21CS01/11 will respond by concurrently driving SI/O low. The device will
continue to drive SI/O low for a total time of t
DACK
. The master should sample the state of the SI/O line at
t
MSDR
past the initiation of t
DRR
. By definition, the t
DACK
minimum is longer than the t
MSDR
maximum time,
thereby ensuring the master can always correctly sample the SI/O for a level less than V
IL
. After the t
DACK
time has elapsed, the AT21CS01/11 will release SI/O which will then be pulled high by the external
pull‑up resistor.
The master must then wait t
HTSS
to create a Start condition before continuing with the first command (see
Start/Stop Condition for more details about Start conditions). By default, the device will come out of Reset
in High-Speed mode. Changing the device to Standard Speed mode is covered in Standard Speed Mode
(Opcode Dh). The AT21CS01/11 will power-up with its internal Address Pointer set to zero.
The timing requirements for the Reset and Discovery Response sequence for both Standard Speed and
High-Speed mode can be found in AT21CS01/11 AC Characteristics.
3.1.2 Interrupting the Device during an Active Operation
To conserve the stored energy within the onboard parasitic power system and minimize overall active
current, the AT21CS01/11 will not monitor the SI/O line for new commands while it is busy executing a
previously sent command. As a result, the device is not able to sense how long SI/O has been in a given
state. If the master requires to interrupt the device during an active operation, it must drive SI/O low long
enough to deplete all of its remaining stored power. This time is defined as t
DSCHG
, after which a normal
Discovery Response can begin by releasing the SI/O line.
Figure 3-1. Reset and Discovery Response Waveform
SI/O
t
RESET
/ t
DSCHG
V
IL
V
IH
MASTER PULL-UP RESISTORAT21CS01
Begin Next
Command with
Start Condition
t
RRT
t
DACK
t
MSDR
Master
Sampling
Window
t
DRR
t
PUP
t
HTSS
AT21CS01/AT21CS11
© 2017 Microchip Technology Inc.
Datasheet
DS20005857A-page 13
3.1.3 Data Input and Output Bit Frames
Communication with the AT21CS01/11 is conducted in time intervals referred to as a bit frame and lasts
t
BIT
in duration. Each bit frame contains a single binary data value. Input bit frames are used to transmit
data from the master to the AT21CS01/11 and can either be a logic ‘0’ or a logic ‘1’. An output bit frame
carries data from the AT21CS01/11 to the master. In all input and output cases, the master initiates the bit
frame by driving the SI/O line low. Once the AT21CS01/11 detects the SI/O being driven below the V
IL
level, its internal timing circuits begin to run.
The duration of each bit frame is allowed to vary from bit to bit as long as the variation does not cause the
t
BIT
length to exceed the specified minimum and maximum values (see AT21CS01/11 AC
Characteristics). The t
BIT
requirements will vary depending on whether the device is set for Low-Speed or
High-Speed mode. For more information about setting the speed of the device, refer to Setting the Device
Speed.
3.1.3.1 Data Input Bit Frames
A data input bit frame can be used by the master to transmit either a logic ‘0’ or logic ‘1’ data bit to the
AT21CS01/11. The input bit frame is initiated when the master drives the SI/O line low. The length of time
that the SI/O line is held low will dictate whether the master is transmitting a logic ‘0’ or a logic ‘1’ for that
bit frame. For a logic ‘0’ input, the length of time that the SI/O line must be held low is defined as t
LOW0
.
Similarly, for a logic ‘1’ input, the length of time that the SI/O line must be held low is defined as t
LOW1
.
The AT21CS01/11 will sample the state of the SI/O line after the maximum t
LOW1
but prior to the minimum
t
LOW0
after SI/O was driven below the V
IL
threshold to determine if the data input is a logic ‘0’ or a
logic ‘1’. If the master is still driving the line low at the sample time, the AT21CS01/11 will decode that bit
frame as a logic ‘0’ as SI/O will be at a voltage less than V
IL
. If the master has already released the SI/O
line, the AT21CS01/11 will see a voltage level greater than or equal to V
IH
because of the external pull-up
resistor, and that bit frame will be decoded as a logic ‘1’. The timing requirements for these parameters
can be found in AT21CS01/11 AC Characteristics.
A logic ‘0’ condition has multiple uses in the I
2
C emulation sequences. It is used to signify a ‘0’ data bit,
and it also is used for an Acknowledge (ACK) response. Additionally, a logic ‘1’ condition is also is used
for a No Acknowledge (NACK) response in addition to the nominal ‘1‘ data bit.
Figure 3-2 and Figure 3-3 depict the logic ‘0’ and logic ‘1’ input bit frames.
Figure 3-2. Logic 0 Input Condition Waveform
SI/O
t
LOW0
V
IL
V
IH
t
BIT
MASTER PULL-UP RESISTOR
t
RCV
AT21CS01/AT21CS11
© 2017 Microchip Technology Inc.
Datasheet
DS20005857A-page 14
Figure 3-3. Logic 1 Input Condition Waveform
SI/O
t
LOW1
V
IL
V
IH
t
BIT
MASTER PULL-UP RESISTOR
3.1.3.2 Start/Stop Condition
All transactions to the AT21CS01/11 begin with a Start condition; therefore, a Start can only be
transmitted by the master to the slave. Likewise, all transactions are terminated with a Stop condition and
thus a Stop condition can only be transmitted by the master to the slave.
The Start and Stop conditions require identical biasing of the SI/O line. The Start/Stop condition is
created by holding the SI/O line at a voltage of V
PUP
for a duration of t
HTSS
. Refer to AT21CS01/11 AC
Characteristics for timing minimums and maximums.
Figure 3-4 and Figure 3-5 depict the Start and Stop conditions.
Figure 3-4. Start Condition Waveform
SI/O
V
IL
V
IH
t
HTSS
MASTER PULL-UP RESISTOR
Figure 3-5. Stop Condition Waveform
3.1.3.3 Communication Interruptions
In the event that a protocol sequence is interrupted midstream, this sequence can be resumed at the
point of interruption if the elapsed time of inactivity (where SI/O is idle) is less that the maximum t
BIT
time.
The maximum allowed value will differ if the device is High-Speed mode or Low-Speed mode (see Setting
the Device Speed).
AT21CS01/AT21CS11
© 2017 Microchip Technology Inc.
Datasheet
DS20005857A-page 15
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AT21CS01-SSHM11-T

Mfr. #:
Buy AT21CS01-SSHM11-T
Manufacturer:
Microchip Technology / Atmel
Description:
EEPROM SEEPROM, 1K, SW - 1.7-3.6V, 125Kbps, Ind Tmp, 8-SOIC
Lifecycle:
New from this manufacturer.
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