AT21CS01-SSHM11-T Datasheet AT21CS01-SSHM11-T, AT21CS01-STUM14-T, AT21CS01-SSHM17-T | P22-P24

6. Write Operations

All write operations for the AT21CS01/11 begin with the master sending a Start condition, followed by a

device address byte (opcode Ah for the EEPROM and opcode Bh for the Security register) with the R/W

bit set to ‘0’ followed by the memory address byte. Next, the data value(s) to be written to the device are

sent. Data values must be sent in 8-bit increments to the device followed by a Stop condition. If a Stop

condition is sent somewhere other than at the byte boundary, the current write operation will be aborted.

The AT21CS01/11 allows single byte writes, partial page writes, and full page writes.

6.1 Device Behavior During Internal Write Cycle

To ensure that the address and data sent to the device for writing are not corrupted while any type of

internal write operation is in progress, commands sent to the device are blocked from being recognized

until the internal operation is completed. If a write interruption occurs (SI/O pulsed low) and is small

enough to not deplete the internal power storage, the device will NACK signaling that the operation is in

progress. If an interruption is longer than t

DSCHG

then internal write operation will be terminated and may

result in data corruption.

6.2 Byte Write

The AT21CS01/11 supports writing of a single 8-bit byte and requires a 7-bit memory word address to

select which byte to write.

Upon receipt of the proper device address byte (with opcode of Ah) and memory address byte, the

EEPROM will send a logic ‘0’ to signify an ACK. The device will then be ready to receive the data byte.

Following receipt of the complete 8-bit data byte, the EEPROM will respond with an ACK. A Stop

condition must then occur; however, since a Stop condition is defined as a null bit frame with SI/O pulled

high, the master does not need to drive the SI/O line to accomplish this. If a Stop condition is sent at any

other time, the write operation is aborted. After the Stop condition is complete, the EEPROM will enter an

internally self-timed write cycle, which will complete within a time of t

, while the data is being

programmed into the nonvolatile EEPROM. The SI/O pin must be pulled high via the external pull-up

resistor during the entire t

cycle. After the maximum t

time has elapsed, the master may begin a

new bus transaction.

Note:

1. Any attempt to interrupt the internal write cycle by driving the SI/O line low may cause the byte

being programmed to be corrupted. Other memory locations within the memory array will not be

affected. Note Device Behavior During Internal Write Cycle for the behavior of the device while the

write cycle is in progress. If the master must interrupt a write operation, the SI/O line must be driven

low for t

DSCHG

as noted in Interrupting the Device during an Active Operation.

Figure 6-1. Byte Write

SI/O

MSB

ACK

by Slave

1 0 1 0 A2 A1 A0 0

Device Address

MSB

x A6 A5 A4 A3 A2 A1 A0

Memory Address

MSB

D D D D D D D D

Data In Byte

ACK

by Slave

`ACK

by Slave

Stop Condition

by Master

Start Condition

by Master

0 0 0

Note:

1. x = Don’t Care bit in the place of A7 as this bit falls outside the 1-Kbit addressable range.

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 22

6.3 Page Write

A page write operation allows up to eight bytes to be written in the same write cycle, provided all bytes

are in the same row (address bits A6 through A3 are the same) of the memory array. Partial page writes

of less than eight bytes are allowed.

A page write is initiated the same way as a byte write, but the bus master does not send a Stop condition

after the first data byte is clocked in. Instead, after the EEPROM acknowledges receipt of the first data

byte, the bus master can transmit up to an additional seven data bytes.

The EEPROM will respond with an ACK after each data byte is received. Once all data bytes have been

sent, the device requires a Stop condition to begin the write cycle. However, since a Stop condition is

defined as a null bit frame with SI/O pulled high, the master does not need to drive the SI/O line to

accomplish this. If a Stop condition is sent at any other time, the write operation is aborted. After the Stop

condition is complete, the internally self-timed write cycle will begin.The SI/O pin must be pulled high via

the external pull-up resistor during the entire t

cycle. Thus, in a multi‑slave environment,

communication to other single-wire devices on the bus should not be attempted while any devices are in

an internal write cycle.

The lower three bits of the memory address are internally incremented following the receipt of each data

byte. The higher order address bits are not incremented, and the device retains the memory page

location. Page write operations are limited to writing bytes within a single physical page, regardless of the

number of bytes actually being written. When the incremented word address reaches the page boundary,

the address counter will “roll over” to the beginning of the same page. Nevertheless, creating a roll over

event should be avoided as previously loaded data in the page could become unintentionally altered.

After the maximum t

time has elapsed, the master may begin a new bus transaction.

Note:

1. Any attempt to interrupt the internal write cycle by driving the SI/O line low may cause the bytes

being programmed to be corrupted. Other memory locations within the memory array will not be

affected. Note Device Behavior During Internal Write Cycle for the behavior of the device while the

write cycle is in progress. If the master must interrupt a write operation, the SI/O line must be driven

low for t

DSCHG

as noted in Interrupting the Device during an Active Operation.

Figure 6-2. Page Write

SI/O

MSB

ACK

by Slave

1 0 1 0 A2 A1 A0 0

Device Address

MSB

x A6 A5 A4 A3 A2 A1 A0

Memory Address

MSB

D D D D D D D D

Data In Byte (1)

D D D D D D D D

Data In Byte (8)

ACK

by Slave

ACK

by Slave

ACK

by Slave

Stop Condition

by Master

Start Condition

by Master

Note:

1. x = Don’t Care bit in the place of A7 as this bit falls outside the 1-Kbit addressable range.

6.4 Writing to the Security Register

The Security register supports bytes writes, page writes, and partial page writes in the upper 16 bytes

(upper two pages of eight bytes each) of the region. Page writes and partial page writes in the Security

EEPROM.

Upon receipt of the proper device address byte (with opcode of Bh specified) and memory address byte,

the EEPROM will send a logic ‘0’ to signify an ACK. The device will then be ready to receive the first data

byte.

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 23

Following receipt of the data byte, the EEPROM will respond with an ACK and the master can send up to

an additional seven bytes if desired. The EEPROM will respond with an ACK after each data byte is

successfully received. Once all of the data bytes have been sent, the device requires a Stop condition to

begin the write cycle. However, since a Stop condition is defined as a null bit frame with SI/O pulled high,

the master does not need to drive the SI/O line to accomplish this. After the Stop condition is complete,

the EEPROM will enter an internally self-timed write cycle, which will complete within a time of t

, while

the data is being programmed into the nonvolatile EEPROM. The SI/O pin must be pulled high via the

external pull-up resistor during the entire t

cycle. Figure 6-3 is included below as an example of a byte

write operation in the Security register.

Figure 6-3. Byte Write in the Security Register

SI/O

MSB

ACK

by Slave

1 0 1 1 A2 A1 A0 0

Device Address

MSB

x x x 1 A3 A2 A1 A0

MSB

D D D D D D D D

Data In Byte

ACK

by Slave

ACK

by Slave

Stop Condition

by Master

Start Condition

by Master

0 0 0

Security Register Address

Note:

1. x = Don’t Care values in the place of A7‑A5 as these bits falls outside the addressable range of the

Security register.

2. Any attempt to interrupt the internal write cycle by driving the SI/O line low may cause the byte

being programmed to be corrupted. Other memory locations within the memory array will not be

affected. Note Device Behavior During Internal Write Cycle for the behavior of the device while the

write cycle is in progress. If the master must interrupt a write operation, the SI/O line must be driven

low for t

DSCHG

as noted in Interrupting the Device during an Active Operation.

6.5 Locking the Security Register

The Lock command is an irreversible sequence that will permanently prevent all future writing to the

upper 16 bytes of the Security register on the AT21CS01/11. Once the Lock command has been

executed, the entire 32-byte Security register becomes read-only. Once the Security register has been

locked, it is not possible to unlock it.

The Lock command protocol emulates a byte write operation to the Security register, however, the

opcode 0010b (2h) is required along with the A7 through A4 bits of the memory address being set to

0110b (6h). The remaining bits of the memory address, as well as the data byte are "don’t care" bits.

Even though these bits are "don’t cares", they still must be transmitted to the device. An ACK response to

the memory address and data byte indicates the Security register is not currently locked. A NACK

response indicates the Security register is already locked. Refer to Figure 6-5 for details about

determining the Lock status of the Security register.

The sequence completes with a Stop condition to initiate a self-timed internal write cycle. If a Stop

condition is sent at any other time, the Lock operation is aborted. Since a Stop condition is defined as a

null bit frame with SI/O pulled high, the master does not need to drive the SI/O line to accomplish this.

Upon completion of the write cycle, (taking a time of t

), the Lock operation is complete and the Security

Note:

1. Any attempt to drive the SI/O line low during the t

time period may cause the Lock operation to

not complete successfully, and must be avoided.

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 24

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AT21CS01-SSHM11-T

Mfr. #:

Buy AT21CS01-SSHM11-T

Manufacturer:

Microchip Technology / Atmel

Description:

EEPROM SEEPROM, 1K, SW - 1.7-3.6V, 125Kbps, Ind Tmp, 8-SOIC

Lifecycle:

New from this manufacturer.

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AT21CS01-SSHM11-T

AT21CS01-SSHM11-T

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