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AT21CS01-SSHM11-T

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Figure 6-4. Lock Command
SI/O
MSB
ACK
by Slave
0 0 1 0 A2 A1 A0 0
Device Address
MSB
0 1 1 0 X X X X
Lock Security Register Address
MSB
X X X X X X X X
Data In Byte
ACK
by Slave
ACK
by Slave
Stop Condition
by Master
Start Condition
by Master
0 0 0
6.5.1 Device Response to a Write Command on a Locked Device
A locked device will respond differently to a Write command to the Security register compared to a device
that has not been locked. Writing to the Security register is accomplished by sending a Start condition
followed by a device address byte with the opcode of 1011b (Bh), the appropriate slave address
combination, and the Read/Write bit set as a logic ‘0’. Both a locked device and a device that has not
been locked will return an ACK. Next, the 8-bit word address is sent and again, both devices will return an
ACK. However, upon sending the data input byte, a device that has already been locked will return a
NACK and be immediately ready to accept a new command, whereas a device that has not been locked
will return an ACK to the data input byte as per normal operation for a Write command as described in
Write Operations.
6.5.2 Check Lock Command
The Check Lock command follows the same sequence as the Lock command (including 0110b in the A7
through A4 bits of the memory address byte) with the exception that only the device address byte and
memory address byte need to be transmitted to the device. An ACK response to the memory address
byte indicates that the lock has not been set while a NACK response indicates that the lock has been set.
If the lock has already been enabled, it cannot be reversed. The Check Lock command is completed by
the master sending a Stop bit to the device (defined as a null bit frame).
Figure 6-5. Check Lock Command
SI/O
MSB
ACK
by Slave
0 0 1 0 A2 A1 A0 0
Device Address
MSB
0 1 1 0 X X X X
Lock Security Register Address
ACK by Slave
if Unlocked
NACK by Slave
if Locked
Stop Condition
by Master
Start Condition
by Master
0
6.6 Setting the Device Speed
The AT21CS01 can be set to Standard Speed mode (15.4 kbps maximum) or High-Speed mode
(125 kbps maximum) through a software sequence. Upon executing a Reset and Discovery Response
sequence (see Device Reset/Power-up and Discovery Response), the device will default to High-Speed
mode. The AT21CS11 does not have Standard Speed mode.
6.6.1 Standard Speed Mode (AT21CS01)
The AT21CS01 can be set to Standard Speed mode or checked to see whether or not it is in Standard
Speed mode with the use of the Dh opcode. This transaction only requires eight bits.
To set the device to Standard Speed mode, the master must send a Start condition, followed by the
device address byte with the opcode of 1101b (Dh) specified, along with the appropriate slave address
combination and the Read/
Write bit set to a logic ‘0’. The device will return an ACK (logic ‘0’) and will be
immediately ready to receive commands for standard speed operation.
AT21CS01/AT21CS11
© 2017 Microchip Technology Inc.
Datasheet
DS20005857A-page 25
To determine if the device is already set to Standard Speed mode, the device address byte with the
opcode of 1101b (Dh) must be sent to the device, along with the appropriate slave address combination
and the Read/Write bit set to a logic ‘1’. The device will return an ACK (logic ‘0’) if it was set for Standard
Speed mode. It will return a NACK (logic ‘1’) if the device was not currently set for Standard Speed mode.
Note:  The AT21CS11 will NACK this command.
6.6.2 High-Speed Mode
The device can be set to High-Speed mode or checked to see whether or not it is in High-Speed mode
with the use of the Eh opcode. This transaction only requires eight bits. The power-on default for the
AT21CS01/11 is High-Speed mode.
To set the device to High-Speed mode, the master must send a Start condition, followed by the device
address byte with the opcode of 1110b (Eh) specified, along the appropriate slave address combination
and the Read/Write bit set to a logic ‘0’. The device will return an ACK (Logic 0) and will be immediately
ready to receive commands for high-speed operation.
To determine if the device is already set to High-Speed mode, the device address byte with the opcode of
1110b (Eh) specified must be sent to the device along with the appropriate slave address combination
and the Read/
Write bit set to a logic ‘1’. The device will return an ACK (logic ‘0’) if it was set for High-
Speed mode. It will return a NACK (logic ‘1’) if the device was not currently set for High-Speed mode.
Note:  The AT21CS11 will ACK this command.
AT21CS01/AT21CS11
© 2017 Microchip Technology Inc.
Datasheet
DS20005857A-page 26
7. Read Operations
Read operations are initiated in a similar way as write operations with the exception that the Read/Write
select bit in the device address byte must be set to a logic ‘1’. There are multiple read operations
supported by the device:
• Current Address Read within the EEPROM
• Random Read within the EEPROM
• Sequential Read within the EEPROM
• Read from the Security Register
• Manufacturer ID Read
Note: 
1. The AT21CS01/11 contains a single, shared-memory Address Pointer that maintains the
address of the next byte in the EEPROM or Security register to be accessed. For example, if
the last byte read or written was memory location 0Dh of the EEPROM, then the Address
Pointer will be pointing to memory location 0Eh of the EEPROM. As such, when changing
from a read in one region to the other, the first read operation in the new region should begin
with a random read instead of a current address read to ensure the Address Pointer is set to
a known value within the desired region.
If the end of the EEPROM or the Security register is reached, then the Address Pointer will “roll over”
back to the beginning (address 00h) of that region. The Address Pointer retains its value between
operations as long as the pull-up voltage on the SI/O pin is maintained or as long as the device has not
been reset.
7.1 Current Address Read within the EEPROM
The internal Address Pointer must be pointing to a memory location within the EEPROM in order to
perform a current address read from the EEPROM. To initiate the operation, the master must send a Start
condition, followed by the device address byte with the opcode of 1010b (Ah) specified, along with the
appropriate slave address combination and the Read/Write bit set to a logic ‘1’. After the device address
byte has been sent, the AT21CS01/11 will return an ACK (logic ‘0’).
Following the ACK, the device is ready to output one byte (eight bits) of data. The master initiates the all
bits of data by driving the SI/O line low to start. The AT21CS01/11 will hold the line low after the master
releases it to indicate a logic ‘0’. If the data is logic ‘1’, the AT21CS01/11 will not hold the SI/O line low at
all, causing it to be pulled high by the pull-up resistor once the master releases it. This sequence repeats
for eight bits.
After the master has read the first data byte and no further data is desired, the master must return a
NACK (logic ‘1’) response to end the read operation and return the device to the Standby mode. Figure
7-1 depicts this sequence.
If the master would like the subsequent byte, it would return an ACK (logic ‘0’) and the device will be
ready output the next byte in the memory array. Refer to Sequential Read within the EEPROM for details
about continuing to read beyond one byte.
Note: 
1. If the last operation to the device was an access to the Security register, then a random read should
be performed to ensure that the Address Pointer is set to a known memory location within the
EEPROM.
AT21CS01/AT21CS11
© 2017 Microchip Technology Inc.
Datasheet
DS20005857A-page 27
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AT21CS01-SSHM11-T

Mfr. #:
Buy AT21CS01-SSHM11-T
Manufacturer:
Microchip Technology / Atmel
Description:
EEPROM SEEPROM, 1K, SW - 1.7-3.6V, 125Kbps, Ind Tmp, 8-SOIC
Lifecycle:
New from this manufacturer.
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