Note: The interruption of protocol must not occur during a write sequence immediately after a logic ‘0’
“ACK” response when sending data to be written to the device. In this case, the interruption will be
interpreted as a Stop condition and will cause an internal write cycle to begin. The device will be busy for
t
WR
time and will not respond to any commands.
Note: For systems that cannot accurately monitor the location of interrupts, it is recommended to ensure
that a minimum interruption time be observed consistent with the longest busy operation of the device
(t
WR
). Communicating with the device while it is in an internal write cycle by the master driving SI/O low
could cause the byte(s) being written to become corrupted and must be avoided. The behavior of the
device during a write cycle is described in more detail in Device Behavior During Internal Write Cycle.
If the sequence is interrupted for longer than the maximum t
BIT
, the master must wait at least the
minimum t
HTSS
before continuing. By waiting the minimum t
HTSS
time, a new Start condition is created
and the device is ready to receive a new command. It is recommended that the master start over and
repeat the transaction that was interrupted midstream.
3.1.3.4 Data Output Bit Frame
A data output bit frame is used when the master is to receive communication back from the
AT21CS01/11. Data output bit frames are used when reading any data out as well as any ACK or NACK
responses from the device. Just as in the input bit frame, the master initiates the sequence by driving the
SI/O line below the V
IL
threshold which engages the AT21CS01/11 internal timing generation circuit.
Within the output bit frame is the critical timing parameter t
RD
, which is defined as the amount of time the
master must continue to drive the SI/O line low after crossing the below V
IL
threshold to request a data bit
back from the AT21CS01/11. Once the t
RD
duration has expired, the master must release the SI/O line.
If the AT21CS01/11 is responding with a logic ‘0’ (for either a ‘0’ data bit or an ACK response), it will begin
to pull the SI/O line low concurrently during the t
RD
window and continue to hold it low for a duration of
t
HLD0
, after which it will release the line to be pulled back up to V
PUP
(see Figure 3-6). Thus, when the
master samples SI/O within the t
MRS
window, it will see a voltage less than V
IL
and decode this event as a
logic ’0’. By definition, the t
HLD0
time is longer than the t
MRS
time and therefore, the master is ensured to
sample while the AT21CS01/11 is still driving the SI/O line low.
Figure 3-6. Logic 0 Data Output Bit Frame Waveform
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
10
3.1.3.4 Data Output Bit Frame
A data output Bit Frame is used when the Master is to receive communication back from the AT21CS01. Data
output Bit Frames are used when reading any data out as well as any ACK or NACK responses from the device.
Just as in the input Bit Frame, the Master initiates the sequence by driving the SI/O line below the V
IL
threshold
which engages the AT21CS01’s internal timing generation circuit.
Within the output Bit Frame is the critical timing parameter t
RD
, which is defined as the amount of time the
Master must continue to drive the SI/O line low after crossing the below V
IL
threshold to request a data bit back
from the AT21CS01. Once the t
RD
duration has expired, the Master must release the SI/O line.
If the AT21CS01 is responding with a Logic 0 (for either a ‘0’ data bit or an ACK response), it will begin to pull
the SI/O line low concurrently during the t
RD
window and continue to hold it low for a duration of t
HLD0
, after
which it will release the line to be pulled back up to V
PUP
(see Figure 3-6). Thus, when the Master samples SI/O
within the t
MRS
window, it will see a voltage less than V
IL
and decode this event as a Logic 0. By definition, the
t
HLD0
time is longer than the t
MRS
time and therefore the Master is guaranteed to sample while the AT21CS01 is
still driving the SI/O line low.
Figure 3-6. Logic 0 Data Output Bit Frame Waveform
If the AT21CS01 intends to respond with a Logic 1 (for either a ‘1’ data bit or a NACK response), it will not drive
the SI/O line low at all. Once the Master releases the SI/O line after the maximum t
RD
has elapsed, the line will
be pulled up to V
PUP
. Thus when the Master samples the SI/O line within the t
MRS
window, it will detect a voltage
greater than V
IH
and decode this event as a Logic 1.
The data output Bit Frame is shown in greater detail below in Figure 3-7.
Figure 3-7. Logic 1 Data Output Bit Frame Waveform
SI/O
V
IL
V
IH
t
BIT
MASTER PULL-UP RESISTOR
t
MRS
t
RCV
AT21CS01
Master
Sampling
Window
t
RD
t
HLD0
t
PUP
SI/O
V
IL
V
IH
t
BIT
MASTER PULL-UP RESISTOR
t
MRS
AT21CS01
Master
Sampling
Window
t
RD
t
PUP
Note: AT21CS01 will not drive the SI/O line during a Logic 1 output Bit Frame.
If the AT21CS01/11 intends to respond with a logic ‘1’ (for either a ‘1’ data bit or a NACK response), it will
not drive the SI/O line low at all. Once the master releases the SI/O line after the maximum t
RD
has
elapsed, the line will be pulled up to V
PUP
. Thus, when the master samples the SI/O line within the t
MRS
window, it will detect a voltage greater than V
IH
and decode this event as a logic ‘1’.
The data output bit frame is shown in greater detail below in Figure 3-7.
AT21CS01/AT21CS11
© 2017 Microchip Technology Inc.
Datasheet
DS20005857A-page 16
