COMMERCIAL TEMPERATURE RANGE
IDTCV105E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
1
JANUARY 2004
IDTCV105E
COMMERCIAL TEMPERATURE RANGE
CLOCK GENERATOR FOR
DESKTOP PC PLATFORMS
XTAL
Osc Amp
SM Bus
Controller
Watch Dog
Timer
Control
Logic
CPU CLK
Output Buffers
3V66/PCI
Output Buffers
SRC CLK
Output Buffer
48MHz
Output Buffer
X1
X2
SDATA
SCLK
V
TT_PWRGD
FS[1:0]
S
EL24_48#
I
REF
IREF
CPU[1:0]
CPU_ITP
REF 1.0
PCI[5:0], PCIF[2:0]
3V66[3:0]
SRC
48MHz[1:0]
PLL3
SSC
PLL4
PLL1
SSC
EasyN
Programming
PLL2
SSC
EasyN
Programming
RESET#
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2004 Integrated Device Technology, Inc. DSC-6392/14
FEATURES:
• 4 PLL architecture
• Linear frequency programming
• Independent frequency programming and SSC control
• Band-gap circuit for differential output
• High power-noise rejection ratio
• 66MHz to 533MHz CPU frequency
• VCO frequency up to 1.1G
• Support index block read/write, single cycle index block read
• Programmable REF, 3V66, PCI, 48MHz I/O drive strength
• Programmable 3V66 and PCI Skew
• Available in SSOP package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
IDTCV105E is a 48 pin clock generation device for desktop PC platforms.
This chip incorporates four PLLs to allow independent generation of CPU, AGP/
PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock
provides high accuracy frequency. This device also implements Band-gap
referenced IREF to reduce the impact of VDD variation on differential outputs,
which can provide more robust system performance.
Static PLL frequency divide error can be as low as 36 ppm, providing high
accuracy output clock. Each CPU, AGP/PCI, SRC clock has its own Spread
Spectrum selection.
KEY SPECIFICATION:
• CPU/SRC CLK cycle to cycle jitter < 125ps
• SATA CLK cycle to cycle jitter < 125ps
• PCI CLK cycle to cycle jitter < 250ps
• Static PLL frequency divide error as low as 36 ppm
OUTPUT TABLE
CPU (Pair) 3V66 3V66/VCH PCI PCIF REF 48MHz 24 - 48MHz SRC (Pair) Reset#
3316322 0 11
