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IDTCV105EPVG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
COMMERCIAL TEMPERATURE RANGE
10
IDTCV105E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
BYTE 24
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 WDHRB WD hard alarm status read back R
6 WDSRB WD soft alarm status read back R
5
4
3
2 0
1 FSR1 HW FS1 read back R HW FS1
0 FSR0 HW FS0 read back R HW FS0
BYTE 25: CPU PLL CONTROL
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 CPU frequency band source select 0 = selected by HW latched FS[1:0], CFS[2:0] HW SW RW 0
1 = selected by BS[2:0], CFS[2:0]
6 BS2, Band select 2 BS[2:0] CFS[2:0] select CPU frequency
(1)
RW 0
5 BS1, Band select 1 BS[2:0] CFS[2:0] select CPU frequency
(1)
RW 0
4 BS0, Band select 0 BS[2:0] CFS[2:0] select CPU frequency
(1)
RW 0
3 CFS2 BS[2:0] CFS[2:0] select CPU frequency
(1)
RW 0
2 CFS1 BS[2:0] CFS[2:0] select CPU frequency
(1)
RW 0
1 CFS0 BS[2:0] CFS[2:0] select CPU frequency
(1)
RW 0
0 CPU N Programming Enable CPU N Programming Enable Disable Enable RW 0
NOTES:
1. See SW FREQUENCY SELECTION table.
BYTE 23
Bit Output(s) Affected Description/Function 0 1 Type Power On Recommended
7 48MHz0 Output enable Tristate Enable RW 1
6 Output enable Tristate Enable RW 1 0
5 REF1 Output enable Tristate Enable RW 1
4 REF0 Output enable Tristate Enable RW 1
3 Reserve 10
2 48MHz1 Output enable Tristate Enable RW 1
1 Output enable Tristate Enable RW 1 0
0 Reserve 0
COMMERCIAL TEMPERATURE RANGE
IDTCV105E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
11
BYTE 26: CPU PLL CONTROL
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 WDBS2 At the event of WD hard alarm time out, RW 1
6 WDBS1 If Byte 32 bit 7 = 1, CPU frequency is RW 0
5 WDBS0 selected by WDBS[2:0] WDCFS[2:0]
(1)
RW 0
4 CSMC2 CPU SMC2, SMC table RW 0
3 CSMC1 CPU SMC1, SMC table RW 1
2 CSMC0 CPU SMC0, SMC table RW 0
1 CPN9 CPU PLL N9 RW 0
0 CPN8 CPU PLL N8 RW 1
NOTE:
1. See SW FREQUENCY SELECTION table.
BYTE 27: CPU PLL N PROGRAMMING
In CPU N programming mode, CPU frequency = CPN[9:0] * band resolution. CPN0 has to be written for the CPN[9:0] to be loaded into PLL N divider. See
SW FREQUENCY SELECTION table.
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 CPN7 CPU PLL N7 RW 0
6 CPN6 CPU PLL N6 RW 0
5 CPN5 CPU PLL N5 RW 1
4 CPN4 CPU PLL N4 RW 0
3 CPN3 CPU PLL N3 RW 1
2 CPN2 CPU PLL N2 RW 0
1 CPN1 CPU PLL N1 RW 1
0 CPN0 CPU PLL N0 RW 0
BYTE 28: AGP/PCI PLL CONTROL
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 AFS2 See AGP/PCI FREQUENCY SELECTION table RW 0
6 AFS1 See AGP/PCI FREQUENCY SELECTION table RW 0
5 AFS0 See AGP/PCI FREQUENCY SELECTION table RW 0
4 WDAFS2 AGP/PCI WD hard alarm time out frequency selection RW 0
3 WDAFS1 AGP/PCI WD hard alarm time out frequency selection RW 0
2 WDAFSO AGP/PCI WD hard alarm time out frequency selection RW 0
1 APN9 AGP/PCI PLL N9 RW 0
0 APN8 AGP/PCI PLL N8 RW 1
COMMERCIAL TEMPERATURE RANGE
12
IDTCV105E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
BYTE 29: AGP/PCI N PROGRAMMING
In AGP/PCI N programming mode, AGP/PCI frequency = APN[9:0] * 0.223721591. APN0 has to be written for the APN[9:0] to be loaded into PLL N divider.
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 APN7 AGP/PCI PLL N7 RW 0
6 APN6 AGP/PCI PLL N6 RW 0
5 APN5 AGP/PCI PLL N5 RW 1
4 APN4 AGP/PCI PLL N4 RW 0
3 APN3 AGP/PCI PLL N3 RW 1
2 APN2 AGP/PCI PLL N2 RW 0
1 APN1 AGP/PCI PLL N1 RW 1
0 APN0 AGP/PCI PLL N0 RW 0
BYTE 30: AGP/PCI SRC CONTROL
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 AGP/PCI N Programming Mode Enable AGP/PCI N Programming Enable Disable Enable RW 0
6 AGP/PCI Frequency Source Select 0 = fixed 66/33MHz 66/33MHz RW 0
1 = selected by AFS[2:0]
(1)
5 AGP SMC 2 AGP/PCI SSC magnitude control
(2)
RW 0
4 AGP SMC 1 AGP/PCI SSC magnitude control
(2)
RW 1
3 AGP SMC 0 AGP/PCI SSC magnitude control
(2)
RW 0
2 3V66-PCI/F skew 2 Adjust 3V66 and PCI/F skew
(3)
RW 0
1 3V66-PCI/F skew 1 Adjust 3V66 and PCI/F skew
(3)
RW 0
0 3V66-PCI/F skew 0 Adjust 3V66 and PCI/F skew
(3)
RW 0
NOTES:
1. See AGP/PCI FREQUENCY SELECTION table.
2. See SMC table.
3. See 3V66 AND PCI/F SKEW table.
BYTE 31: WATCHDOG TIMER
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 WD Hard Alarm timer 7 Specify WD Hard Alarm time out waiting time. RW 0
6 WD Hard Alarm timer 6 Time Out time = WD Hard Alarm timer[7:0] * 290ms RW 0
5 WD Hard Alarm timer 5 Default is 11*290 = 3.2s RW 0
4 WD Hard Alarm timer 4 RW 0
3 WD Hard Alarm timer 3 RW 1
2 WD Hard Alarm timer 2 RW 0
1 WD Hard Alarm timer 1 RW 1
0 WD Hard Alarm timer 0 RW 1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

IDTCV105EPVG8

Mfr. #:
Buy IDTCV105EPVG8
Manufacturer:
Description:
IC CLK GEN DESKTOP PC 48-SSOP
Lifecycle:
New from this manufacturer.
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