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IDTCV105EPVG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
COMMERCIAL TEMPERATURE RANGE
4
IDTCV105E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
PIN DESCRIPTION
Pin Number Name Type Description
1 FS1/REF0 I/O Frequency select latch input 3.3V input HIGH/LOW voltage/ 14.318MHz reference clock output
(1)
2 FS0/REF1 I/O Frequency select latch input 2.5V input HIGH/LOW voltage/ 14.318MHz reference clock output
(1)
3VDD_REF PWR 3.3V
4 X1 IN Xtal input
5 X2 OUT Xtal output
6VSS GND GND
7 PCIF0 I/O Frequency select latch input 3.3V input HIGH/LOW voltage/ PCI free running clock
(2)
8 PCIF1 OUT PCI free running clock
9 PCIF2 OUT PCI free running clock
10 VDD_PCI PWR 3.3V
11 VSS GND GND
12 PCI0 OUT PCI clock
13 PCI1 OUT PCI clock
14 PCI2 OUT PCI clock
15 PCI3 OUT PCI clock
16 VDD_PCI PWR 3.3V
17 VSS GND GND
18 PCI4 OUT PCI clock
19 PCI5 OUT PCI clock
20 RESET#/PD# OUT Reset output signal from watchdog circuit, active LOW/ power down control input. Mode selectable through
SM bus, power on is RESET# mode.
(1)
21 48MHz1 OUT 48MHz clock output
22 48MHz0 OUT 48MHz clock output. Phase is 180 different with 24_48, 48MHz1, and VCH. Output drive stength can
be doubled through SM programming.
23 VSS GND GND
24 VDD48 PWR 3.3V
25 3V66_3/VCH OUT 66MHz or 48MHz clock output. Selectable by SMBus. Power on is 66MHz.
26 3V66_2 OUT 66MHz clock output
27 VDD_3V66 PWR 3.3V
28 VSS GND GND
29 3V66_1 OUT 66MHz clock output
30 3V66_0 OUT 66MHz clock output
31 SCLK IN SMBus clock
(1)
32 SDATA I/O SMBus data
(1)
33 VTT_PWRGD# IN Used for power on latch, active LOW
(1)
34 VDD_SRC PWR 3.3V
35 SRCC OUT SATA 0.7V current mode differential clock output
36 SRCT OUT SATA 0.7V current mode differential clock output
37 VSS GND GND
38 CPU C0 OUT Hosts 0.7V current mode differential clock output
39 CPUT0 OUT Hosts 0.7V current mode differential clock output
40 VDD_CPU PWR 3.3V
NOTES:
1. ~ 130KΩ internal pull-up.
2. ~ 130KΩ internal pull-down.
COMMERCIAL TEMPERATURE RANGE
IDTCV105E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
5
PIN DESCRIPTION (CONT.)
Pin Number Name Type Description
41 CP UC1 OUT Hosts 0.7V current mode differential clock output
42 CPUT1 OUT Hosts 0.7V current mode differential clock output
43 VSS GND GND
44 CPUC_ITP OUT Hosts 0.7V current mode differential clock output
45 CPUT_ITP OUT Hosts 0.7V current mode differential clock output
46 IREF OUT Reference current for differential output
47 VSS GND GND
48 V
DDA PWR 3.3V
COMMERCIAL TEMPERATURE RANGE
6
IDTCV105E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
ONECYCLE™ INDEX BLOCK READ
Bit # of bits From Description
1 1 Master Start
2-9 8 Master D2h
10 1 Slave Acknowledge
11-18 8 Master Register offset byte (starting byte)
19 1 Slave Acknowledge
20-27 8 Master 1xxxxxxx. Bit[20] = 1, followed with byte
count, which will be stored into SMBus table
byte 8.
28 1 Slave Acknowledge
29 1 Master Repeated start
30-37 8 Master D3h
38 1 Slave Acknowledge
39-46 8 Slave Byte count, N, SMBus table byte 8 value.
Power on default is 0FH[15].
47 1 Master Acknowledge
48-55 8 Slave Offset data byte, specified by bit[11:18]
56 1 Master Acknowledge
57-64 8 Slave Offset + 1 data byte
:
Slave Offset + N-2
Master Acknowledge
Slave Offset + N-1
Not acknowledge
Stop
BYTE READ METHODS (CHOSE ONE):
• Use IDT OneCycle Index Block Read, bit[20:27] = 10000001.
Notice that byte count register (byte 8) will be changed to 0IH.
• Use Index Block Write protocol to change byte count (byte 8) to
1. After that, use Index Block Read.
TO CHANGE BYTE 8 VALUE:
• Use IDT OneCycle Index Block Read, as above
• Use Index Block Write protocol to change byte 8 value.
SMBUS PROTOCOL
INDEX BLOCK READ PROTOCOL
Bit # of bits From Description
1 1 Master Start
2-9 8 Master D2h
10 1 Slave Acknowledge
11-18 8 Master Register offset byte (starting byte)
19 1 Slave Acknowledge
20 1 Master Repeated start
21-28 8 Master D3h
29 1 Slave Acknowledge
30-37 8 Slave Byte count, N, SMBus table byte 8 value.
Power on default is 0FH[15].
38 1 Master Acknowledge
39-46 8 Slave Offset data byte, specified by bit 11-18
47 1 Master Acknowledge
48-55 8 Slave Offset + 1 data byte
:
Slave Offset + N-2
Master Acknowledge
Slave Offset + N-1
Not acknowledge
Stop
INDEX BLOCK WRITE PROTOCOL
Bit # of bits From Description
1 1 Master Start
2-9 8 Master D2h
10 1 Slave Acknowledge
11-18 8 Master Register offset byte (starting byte)
19 1 Slave Acknowledge
20-27 8 Master Byte count N (0 is not a valid byte count)
(1)
28 1 Slave Acknowledge
29-36 8 Master First data byte
37 1 Slave Acknowledge
38-45 8 Master Second data byte
46 1 Slave Acknowledge
:
Nth data byte
Stop
NOTE:
1. Bit [21:27] = byte count.
Bit 20 = 1, bit [21:27] will be stored into SMBus table, Byte 8. SMBus Byte 8 is read
byte count register, power on default is 0FH.
Bit 20 = 0, normal SM bus operation.
BYTE WRITE METHODS:
• Setting bit[11:18] = starting address, bit [20:27] = 01H.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

IDTCV105EPVG8

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Buy IDTCV105EPVG8
Manufacturer:
Description:
IC CLK GEN DESKTOP PC 48-SSOP
Lifecycle:
New from this manufacturer.
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