COMMERCIAL TEMPERATURE RANGE
IDTCV105E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
13
BYTE 32: WD SOFT RESET TIMER
WD Soft Alarm timer has to be shorter than WD Hard Alarm timer. WDE and WD Soft Alarm bits, Byte 33 bit 7 and bit 5, have to be enabled for this Soft Alarm
function.
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 CPU WD Hard Alarm 0 = frequency select controlled by Byte 25 bit 7 HW/I2C WDBS RW 0
safe frequency mode select 1 = CPU frequency specified WDCFS
by WDBS[2:0] WDCFS[2:0]
6 WDCFS2 CPU WD time out safe frequency select
(1)
RW 0
5 WDCFS1 RW 0
4 WDCFS0 RW 0
3 WD soft alarm timer 3 Specify WD Soft Alarm Time Out time RW 0
2 WD soft alarm timer 2 Time Out time = WD Soft Alarm Timer[3:0]*290ms RW 0
1 WD soft alarm timer 1 Default is 580ms. RW 1
0 WD soft alarm timer 0 RW 0
NOTE:
1. See SW FREQUENCY SELECTION table.
BYTE 33: WD CONTROL
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 WDE Watchdog enable Disable Enable RW 0
6 WD FS relatch Relatch HW FS2, 1, 0 Disable Enable RW 0
in event of WD Hard Alarm time out
5 WD Soft Alarm enable WD Soft Alarm enable Disable Enable RW 0
4 AGP/PCI WD Hard Alarm In event of WD Hard Alarm time out HW/I2C WDAFS RW 0
time out safe frequency mode select 0 = AGP/PCI frequency controlled by Byte 30 bit 6
1 = AGP/PCI frequency specified by WDAFS[2:0]
3 SRC SMC 2 SRC SSC magnitude control
(1)
1
2 SRC SMC 1 SRC SSC magnitude control
(1)
0
1 SRC SMC 0 SRC SSC magnitude control
(1)
1
0 Reserve 0
BYTE 34
Bit Output(s) Affected Description/Function 0 1 Type Power On
7 SW 24_48MHz control override 0 = controlled by hardware, 1 = controlled by bit 6 HW control controlled by RW 0
bit 6
6 24_48MHz select 48MHz 24MHz RW 0
5 Reset#/PD# Reset#/PD# mode select Reset# PD# RW 0
4 0
3 0
2
1
0
NOTE:
1. See SMC table.
COMMERCIAL TEMPERATURE RANGE
14
IDTCV105E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
CPU AND AGP CLOCK FREQUENCY SELECTION
Band switch will take effect only when WD Soft Alarm time out is issued, which means there is a RESET issued. Even if the user changed BS[2:0], if there
is no WD Soft Alarm, CPU PLL still uses the old band.
CPN[9:0] and APN[9:0] will be loaded into PLL only when CPN0 and APN0 are written respectively.
Byte 32 bit 7, CPU WD Hard Alarm Time Out Frequency Select:
Byte 25 bit 7
00 Latched HW FS[1:0]
01 BS[2:0], CFS[2:0], Byte 25
10 WDBS[2:0], WDCFS[2:0], Byte 26 and Byte 32
11 WDBS[2:0], WDCFS[2:0], Byte 26 and Byte 32
WD SOFT AND HARD ALARM/TIME OUT OPERATION
WD HARD ALARM TIMER [7:0]
WD SOFT ALARM TIMER [3:0]
WDE
Trigger Watch Dog Circuit
WD SOFT ALARM TIME OUT
If WD Soft Alarm Enabled:
Set WDSRB
Issue RESET#
Switch CPU PLL band
WD HARD ALARM TIME OUT
Set WDHRB
Issue RESET#
Change CPU Frequency (see Byte 32, bit 7)
Change AGP/PCI Frequency (see Byte 33, bit 4)
If WD FS Relatch enabled, relatch HW FS2, FS1, FS0
Reset Byte 30 bit 7, and Byte 25 bit 0, to 0
User only uses WD Soft Alarm when there is a band switch. It can be from HW to SW select, or in the SW select with band change. Soft Alarm Timer has
to be shorter than Hard Alarm Timer.
At the event of WD Hard Alarm time out, CPU Safe return frequency is decided by two bits: Byte 32 bit 7 and Byte 25 bit 7. AGP/PCI Safe Return Frequency
is decided by Byte 33 bit 4 and Byte 30 bit 6. Byte 30 bit 7, and Byte 25 bit 0, will be reset to 0.
Byte 33 bit 4, AGP/PCI Hard Alarm Time Out Frequency Select:
Byte 30 bit 6
00 66/33MHz
01 AFS[2:0], Byte 28
10 WDAFS, Byte 28
11 WDAFS, Byte 28
CPU FREQUENCY
Byte 25 bit 0, bit 7 CPU Frequency Selected by:
00 HW FS[1:0]
01 BS[2:0], CFS[2:0], Byte 25
10 CPN[9:0] * Band Resolution
11 CPN[9:0] * Band Resolution
AGP/PCI FREQUENCY
Byte 30 bit 7, bit 6 AGP/PCI Frequency Selected by:
00 66/33
01 AFS[2:0], Byte 28
10 APN[9:0] * 0.223721591
11 APN[9:0] * 0.223721591
COMMERCIAL TEMPERATURE RANGE
IDTCV105E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
15
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIH 3.3V Input HIGH Voltage 3.3V ± 5% 2 VDD + 0.3 V
VIL 3.3V Input LOW Voltage 3.3V ± 5% VSS - 0.3 0.8 V
IIH Input HIGH Current VIN = VDD –5 5 µ A
IIL1 Input LOW Current VIN = 0V, inputs with no pull-up resistors 5 µ A
IIL2 Input LOW Current VIN = 0V, inputs with pull-up resistors –200 µ A
IDD3.3OP Operating Supply Current Full active, CL = full load 400 mA
I
DD3.3PD Powerdown Current All differential pairs driven 70 mA
All differential pairs tri-stated 12
FI Input Frequency
(2)
VDD = 3.3V 14.31818 MHz
LPIN Pin Inductance
(3)
—— 7 nH
CIN Logic inputs 5
COUT Input Capacitance
(3)
Output pin capacitance 6 pF
CINX X1 and X2 pins 5
TSTAB Clock Stabilization
(3,4)
From VDD power-up or de-assertion of PD# to first clock 1.8 ms
Modulation Frequency
(3)
Triangular modulation 30 33 KHz
TDRIVE_SRC
(3)
SRC output enable after PCI_Stop# de-assertion 15 ns
TDRIVE_PD#
(3)
CPU output enable after PD# de-assertion 300 us
TFALL_PD#
(3)
Fall time of PD# 5 ns
TRISE_PD#
(4)
Rise time of PD# 5 ns
TDRIVE_CPU_Stop#
(3)
CPU output enable after CPU_Stop# de-assertion 10 us
TFALL_CPU_Stop#
(3)
Fall time of PD# 5 ns
TRISE_CPU_Stop#
(4)
Rise time of PD# 5 ns
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
NOTES:
1. Available to CV104, CV105, CV107, and CV109.
2. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
3. This parameter is guaranteed by design, but not 100% production tested.
4. See TIMING DIAGRAMS for timing requirements.

IDTCV105EPVG8

Mfr. #:
Manufacturer:
Description:
IC CLK GEN DESKTOP PC 48-SSOP
Lifecycle:
New from this manufacturer.
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