71V2556S150PFG Datasheet 71V2556S166PFG, 71V2556SA100BGG, 71V2556SA133BGG8 | P1-P3

APRIL 2011

DSC-4875/12

Pin Description Summary

Description

The IDT71V2556 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAM. It is designed to eliminate dead bus cycles when

turning the bus around between reads and writes, or writes and reads.

Thus, they have been given the name ZBT

, or Zero Bus Turnaround.

Features

◆◆

◆

128K x 36 memory configurations

◆◆

◆

Supports high performance system speed - 166 MHz

(3.5 ns Clock-to-Data Access)

◆◆

◆

ZBT

Feature - No dead cycles between write and read

cycles

◆◆

◆

Internally synchronized output buffer enable eliminates the

need to control OE

◆◆

◆

Single R/W (READ/WRITE) control pin

◆◆

◆

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

◆◆

◆

4-word burst capability (interleaved or linear)

◆◆

◆

Individual byte write (BW1 - BW4) control (May tie active)

◆◆

◆

Three chip enables for simple depth expansion

◆◆

◆

3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)

◆◆

◆

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

complaint)

◆◆

◆

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP) and 119 ball grid array (BGA)

A-

stupnIsserddAtupnIsuonorhcnyS

EC,

, EC

selbanEpihCtupnIsuonorhcnyS

elbanEtuptuOtupnIsuonorhcnysA

/R W langiSetirW/daeRtupnIsuonorhcnyS

NEC

elbanEkcolCt

upnIsuonorhcnyS

, WB

stceleSetirWetyBlaudividnItupnIsuonorhcnyS

KLCkcolCtupnIA/N

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rhcnyS

OBL

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SMTtceleSedoMtseTtupnIsuonorhcnyS

IDTtupnIataDtseTtupnIsuonorh

cnyS

KCTkcolCtseTtupnIA/N

ODTtuptuOataDtseTtuptuOsuonorhcnyS

TSRT

)lanoitpO(teseRGATJtupnIsuonorhcnysA

ZZedoMpeelStu

pnIsuonorhcnyS

O/I

O/I-

O/I,

O/I-

tuptuO/tupnIataDO/IsuonorhcnyS

QDD

rewoPO/I,rewoPeroCylppuScitatS

dnuorGylppuScitatS

10lbt5784

IDT71V2556S/XS

IDT71V2556SA/XSA

128K x 36

3.3V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

Address and control signals are applied to the SRAM during one clock

cycle, and two cycles later the associated data cycle occurs, be it read

or write.

The IDT71V2556 contains data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be used

to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V2556 to be

suspended as long as necessary. All synchronous inputs are ignored

when (CEN) is high and the internal device registers will hold their previous

values.

There are three chip enable pins (CE1, CE2, CE2) that allow the user

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

The data bus will tri-state two cycles after chip is deselected or a write is

initiated.

The IDT71V2556 has an on-chip burst counter. In the burst mode, the

IDT71V2556 can provide four cycles of data for a single address

presented to the SRAM. The order of the burst sequence is defined by the

LBO input pin. The LBO pin selects between linear and interleaved burst

sequence. The ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =

HIGH).

The IDT71V2556 SRAMs utilize IDT's latest high-performance CMOS

process and are packaged in a JEDEC standard 14mm x 20mm 100-pin

thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA).

6.422

IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Definitions

(1)

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

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, EC

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ro EC

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sah

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nwodlluplanretni

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QDD

ylppuSrewoPA/NA/N.ylppuSO/IV5.2

dnuorGA/NA/N.dnuorG

20lbt5784

6.42

IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram

Clk

Address A [0:16]

Control Logic

Address

Control

DI DO

Input Register

4875 drw 01a

Clock

Data I/O [0:31],

I/O P[1:4]

Clk

Output Register

Mux

Sel

Gate

CE1, CE2, CE2

R/W

CEN

ADV/LD

BWx

LBO

128Kx36 BIT

MEMORY ARRAY

JTAG

(SA Version)

TMS

TDI

TCK

TDO

TRST

(optional)

Recommended DC Operating

Conditions

NOTES:

1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.

2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.

lobmySretemaraP.niM.pyT.xaMtinU

egatloVylppuSeroC531.33.3564.3V

QDD

egatloVylppuSO/I573.25.2526.2V

egatloVylppuS000V

stupnI-egatloVhgiHtupnI7.1

____

3.0+V

egatloVhgiHtupnI-O/I7.1

____

QDD

3.0+

)2(

egatloVwoLtupnI3.0-

)1(

____

7.0V

30lbt5784

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

71V2556S150PFG

Mfr. #:

Buy 71V2556S150PFG

Manufacturer:

IDT

Description:

SRAM 4M X36 2.5V I/O SLOW ZBT

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

71V2556S150PFG

71V2556S150PFG

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