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71V2556S150PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
6.42
4
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Pin Configuration — 128K x 36
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
Top View
TQFP
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
4875 drw 02
V
DD
(1)
I/O
15
I/O
P3
V
DD
(1)
I/O
P4
A
15
A
16
I/O
P1
V
DD
(1)
I/O
P2
V
SS/ZZ
(3)
,
NC
NC
NC
edarGerutarepmeT
)1(
V
SS
V
DD
V
QDD
laicremmoCC°07+otC°0V0%5±V3.3%5±V5.2
lairtsudnIC°58+otC°04-V0%5±V3.3%5±V5.2
50lbt5784
NOTE:
1. T
A is the "instant on" case temperature.
6.42
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
5
Absolute Maximum Ratings
(1)
100 TQFP Capacitance
(1)
(TA = +25° C, f = 1.0MHz)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. TA is the "instant on" case temperature.
lobmySgnitaR
&laicremmoC
seulaVlairtsudnI
tinU
V
MRET
)2(
htiwegatloVlanimreT
DNGottcepseR
6.4+ot5.0-V
V
MRET
)6,3(
htiwegatloVlanimreT
DNGottcepseR
Vot5.0-
DD
V
V
MRET
)6,4(
htiwegatloVlanimreT
DNGottcepseR
Vot5.0-
DD
5.0+V
V
MRET
)6,5(
htiwegatloVlanimreT
DNGottcepseR
Vot5.0-
QDD
5.0+V
T
A
)7(
laciremmoC
erutarepmeTgnitarepO
07+ot0-
o
C
lairtsudnI
erutarepmeTgnitarepO
58+ot04-
o
C
T
SAIB
erutarepmeT
saiBrednU
521+ot55-
o
C
T
GTS
egarotS
erutarepmeT
521+ot55-
o
C
P
T
noitapissiDrewoP0.2W
I
TUO
tnerruCtuptuOCD05Am
60lbt5784
lobmySretemaraP
)1(
snoitidnoC.xaMtinU
C
NI
ecnaticapaCtupnIV
NI
Vd3=5Fp
C
O/I
ecnaticapaCO/IV
TUO
Vd3=7Fp
70lbt5784
119 BGA Capacitance
(1)
(TA = +25° C, f = 1.0MHz)
lobmySretemaraP
)1(
snoitidnoC.xaMtinU
C
NI
ecnaticapaCtupnIV
NI
Vd3=7Fp
C
O/I
ecnaticapaCO/IV
TUO
Vd3=7Fp
a70lbt5784
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.424
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Pin Configuration — 128K x 36
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
Top View
TQFP
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A6
A7
CE1
CE2
BW 4
BW 3
BW 2
BW 1
CE2
V
DD
VSS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A8
A9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
LB O
A
14
A13
A12
A11
A10
VDD
VSS
A0
A1
A2
A3
A4
A5
I/O31
I/O30
VDDQ
VSS
I/O29
I/O28
I/O27
I/O26
VSS
VDDQ
I/O25
I/O24
VSS
VDD
I/O23
I/O22
VDDQ
VSS
I/O21
I/O20
I/O19
I/O18
VSS
VDDQ
I/O17
I/O16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VDD
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
4875 drw 02
VDD
(1)
I/O15
I/OP3
VDD
(1)
I/OP4
A15
A16
I/OP1
VDD
(1)
I/OP2
VSS/ZZ
(3)
,
NC
NC
NC
edarGerutarepmeT
)1(
V
SS
V
DD
V
QDD
laicremmoCC°07+otC°0V0%5±V3.3%5±V5.2
lairtsudnIC°58+otC°04-V0%5±V3.3%5±V5.2
50lbt5784
NOTE:
1. TA is the "instant on" case temperature.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

71V2556S150PFG

Mfr. #:
Buy 71V2556S150PFG
Manufacturer:
IDT
Description:
SRAM 4M X36 2.5V I/O SLOW ZBT
Lifecycle:
New from this manufacturer.
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